Part Number: LMK04828
Other Parts Discussed in Thread: ADS54J66, DAC37J84
Hi,
I would like to ask you some questions about SYSREF of LMK04828 as below.
I am considering to use ADS54J66, DAC37J84 with LMK04828, FPGA is Altela. (SERDES rate is 10G)
Q1) SYSREF cross talk
I am studying following E2E post.
http://e2e.ti.com/support/clocks/m/videos__files/666599
There are SYSREF settings, "Pulsed" (6.b) and "Request" (6.c) on the file.
Which setting is better to minimize "cross talk" against other clock lines?
And could you tell me another way to minimize if you know?
Q2) SYSREF pulse output number
Could you advise me the output number of SYSREF pulses at a time and the interval length between each SYSREF output?
For example, 100mSec interval and over 2 pulses output...
Q3) Register setting of ADC amd DAC
Is it possible to set ADC and DAC registers under outputting SYSREF pulses intermittently?
Or should we output SYSREF continuously under setting the registers and after finished setting begin to output SYSREF intermittently?
Thank you for your support in advance.
Best Regards,