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LMK04828: SYSREF questions

Part Number: LMK04828
Other Parts Discussed in Thread: ADS54J66, DAC37J84

Hi,

I would like to ask you some questions about SYSREF of LMK04828 as below.

I am considering to use ADS54J66, DAC37J84 with LMK04828, FPGA is Altela. (SERDES rate is 10G)

Q1) SYSREF cross talk

I am studying following E2E post.

http://e2e.ti.com/support/clocks/m/videos__files/666599

There are SYSREF settings, "Pulsed" (6.b) and "Request" (6.c) on the file.

Which setting is better to minimize "cross talk" against other clock lines?

And could you tell me another way to minimize if you know?

Q2) SYSREF pulse output number

Could you advise me the output number of SYSREF pulses at a time and the interval length between each SYSREF output?

For example, 100mSec interval and over 2 pulses output...

Q3) Register setting of ADC amd DAC

Is it possible to set ADC and DAC registers under outputting SYSREF pulses intermittently?

Or should we output SYSREF continuously under setting the registers and after finished setting begin to output SYSREF intermittently?

Thank you for your support in advance.

Best Regards,

  • Takumi Suzuki1 said:

    Q1) SYSREF cross talk

    I am studying following E2E post.

    http://e2e.ti.com/support/clocks/m/videos__files/666599

    There are SYSREF settings, "Pulsed" (6.b) and "Request" (6.c) on the file.

    Which setting is better to minimize "cross talk" against other clock lines?

    And could you tell me another way to minimize if you know?

    I think pulsed will be the least chance of crosstalk.  If the SYNC pin toggles a lot (which it shouldn't) or has some noise, it could couple onto VCO0, or to a lessor degree VCO1 and cause a spur.  You may consider an RC filter on SYNC pin.

    Takumi Suzuki1 said:

    Q2) SYSREF pulse output number

    Could you advise me the output number of SYSREF pulses at a time and the interval length between each SYSREF output?

    For example, 100mSec interval and over 2 pulses output...

    You can think of the SYSREF pulser as gating off the requested number of pulses from the SYSREF divider.  So a pulse will come every 1/SYSREF Frequency and the duration of the pulse will be ~0.5/SYSREF Frequency.

    Takumi Suzuki1 said:

    Q3) Register setting of ADC amd DAC

    Is it possible to set ADC and DAC registers under outputting SYSREF pulses intermittently?

    Or should we output SYSREF continuously under setting the registers and after finished setting begin to output SYSREF intermittently?

    Thank you for your support in advance.


    I'm not sure I fully follow you here.  But yes, I think you are able to program the ADC/DAC registers, and then send the SYSREF pulses to align the LMFC between them.  Continuous SYSREF output is not necessary.

    73,
    Timothy

  • Hi Timothy-san,

    Thank you very much! I understood.

    I'm sorry for my late response.

    Best Regards,