Hello,
I am working with a board that uses CDCVF2505 for gated clock distribution. The input clock toggles and stops for some period of time for power savings, but we noticed that occasionally the output clock from the buffer does not have a sharp falling edge and instead is decaying slowly. Blue is the input clock and yellow is the output:
Is this a known issue for this device? Are there any recommendations for mitigating it?
Thank you,
ilya
Hi Sridhar,
Thanks for the response!
Let me get the schematics, at the moment I only have a block diagram that I can share:
We have a master device supplying 33MHz gated clock which then goes to a target device via 1Y1 output and back to the master (to compensate for clock delay on the board) via 1Y3. When clock is gated we always gate it at 0, but looks like the outputs of CDCVF2505 stop at 1 and then decay slowly in some cases. We are monitoring both outputs 1Y1 and 1Y3. Other outputs are not connected on the board.
Thank you Sridhar.
I was able to get the schematics showing the details of other pins. Hope this helps.
CLK_FB is routed as feedback to the master device and CLK_O goes to the target device in this case.
ilya
