• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 21 subscribers
  • Views 1329 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CDCM6208: Power cycling resulting in out of phase clocks

John Fedak
Expert 6715 points
Part Number: CDCM6208

Hi Team,

Good afternoon, my customer has noticed an interesting behavior with the CDCM2608:

Amongst others, I have 120MHz on Y0, Y1, and Y4. In certain modes to save power, I am turning of the power to the VDD_Y0_Y1 and VDD_Y4 pins but not disabling the outputs themselves. If I turn on and off the power repeatedly, the output clocks go out of phase. Do you know why? By disabling the power to the outputs am I putting the device in an unstable state and causing ill effects related to the phase?

 I realize there's a SYNCN pin and also an internal register bit which can also be programmed via SPI. However, I cannot assert this signal because one of the outputs of the CDCM6208 is the system clock and I don't want to mess with that.

Also the SYNCN pin is tied to the RESETN pin. With this, are the outputs in sync when I come out of a reset state?

Is there any way to sync some outputs without affecting others? ie. sync the 120MHz clocks without syncing my system clock.

Please let me know if you have any questions, thank you!

Regards,

~John

  • 0
    TI__Genius 9920 points
    Hi John,
    The target is to save power, we could disable output driver by register control (I2C or SPI mode).
    If customer is using pin mode, we still could use SPI mode if pins were connected.

    Cut power VDD_Y0_Y1 would power off divider, when power up again, divider would restart to count.
    While power up time is random, so divider output edge also would random. Divider by integer N, then there are chances to generate N kinds of clock phase.

    If you still like to cut VDD_Ya_Yb, power up trigger signal should be from CDCM6208.
    The trigger signal should be from a common factor of all frequency need to be SYNCed.

    If the problem had not been solved, I'd like look into customer's CDCM6208 schematic and configuration.

    Regards,
    Shawn
  • 0 in reply to Shawn Han
    TI__Expert 6715 points

    Hi Shawn,

    Thank you - follow-up question on this.

    If we select “PRI” for one of the outputs – I assume this one doesn’t get affected when we do the SYNC, does it?

    Regards,

    ~John

  • 0 in reply to John Fedak
    TI__Genius 9920 points
    Hi John,
    Yes.
    When we select "PRI" or "SEC" for output, the output divider is bybpassed, then SYNC would not affect this output channel.

    Regards,
    Shawn
  • 0 in reply to Shawn Han
    TI__Expert 6715 points
    Hi Shawn,

    This is great to hear!

    Regards,
    ~John
  • 0 in reply to John Fedak
    TI__Genius 9920 points

    This problem had been discussed off line. Post some conclusions here.

    Hi John,

    Y0, Y1 shares one divider, so when we select “disable” for only one channel (Y0 or Y1), the divider still is running, so when return to normal output, the phase would not be changed.

     

    While,

     

    When we disable both Y0 and Y1, CDCM6208 would disable their divider, then turn on the outputs would get different phase than previous.

     

    Y4 has an individual divider, so when “disable” Y4, CDCM6208 also would disable the divider. Then output phase would be changed when the divider restarted.

     

    In this situation, we have to use SYNC to achieve output phase alignment.

    cid:image003.png@01D2CA63.585BA5E0

    But 33M for system should not been muted. We have to choose Y5 from PRI/SEC, which bypass divider, no response to SYNC.

    That's meaning PRI/SEC source should select what we like to get, like 33MHz here.

     

    Regards,

    Shawn