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LMK04828: LMK04828 NESTED 0-DELAY PLL1&PLL2 LOCK DETECT ISSUE

bharath
Intellectual 425 points
Part Number: LMK04828

We are using LMK04828 in nested 0 -delay mode with reference input freq of 25MHz and external VCXO of 100MHz.Attached SPI register file. Whether i am missing any settings of PLL1 & PLL2.

Kindly help me regarding this.

Regards,

Jaya Bharath

Fullscreen LMK04828-0V01nested-delay_ITER_3.txt Download 
R0 (INIT)	0x000090
R0	0x000000
R2	0x000200
R256	0x01006F
R257	0x010100
R259	0x010305
R260	0x010420
R261	0x010510
R262	0x010600
R263	0x010711
R264	0x01087E
R265	0x010900
R267	0x010B05
R268	0x010C20
R269	0x010D10
R270	0x010E00
R271	0x010F01
R272	0x01106F
R273	0x011100
R275	0x011301
R276	0x011420
R277	0x011510
R278	0x011600
R279	0x011717
R280	0x01186F
R281	0x011900
R283	0x011B05
R284	0x011C20
R285	0x011D10
R286	0x011E00
R287	0x011F11
R288	0x01207E
R289	0x012100
R291	0x012305
R292	0x012400
R293	0x012510
R294	0x012600
R295	0x012711
R296	0x012878
R297	0x012900
R299	0x012B04
R300	0x012C00
R301	0x012D10
R302	0x012E00
R303	0x012F11
R304	0x01306F
R305	0x013100
R307	0x013305
R308	0x013420
R309	0x013510
R310	0x013600
R311	0x013711
R312	0x013821
R313	0x013902
R314	0x013A01
R315	0x013B2C
R316	0x013C00
R317	0x013D00
R318	0x013E03
R319	0x013F09
R320	0x014000
R321	0x0141FF
R322	0x014200
R323	0x014311
R324	0x014400
R325	0x01457F
R326	0x014603
R327	0x01473A
R328	0x014800
R329	0x014900
R330	0x014A0A
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015677
R343	0x015700
R344	0x015896
R345	0x015901
R346	0x015ADC
R347	0x015BF4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016106
R354	0x016264
R355	0x016300
R356	0x016400
R357	0x01650C
R380	0x017C15
R381	0x017D33
R358	0x016600
R359	0x016700
R360	0x01683C
R361	0x016959
R362	0x016A60
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017300
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53

  • 0
    TI__Mastermind 28550 points
    Hello,
    What is your specific issue? What is the voltage on CPout1 and CPout2?

    Reviewing the programming based on your frequencies...

    For PLL2, with 100 MHz VCXO....
    VCO Frequency = VCXO Frequency / PLL2_R * PLL2_N * PLL2_P
    VCO Frequency = 100 MHz / 6 * 60 * 3 = 3000 MHz. Confirmed. I expect that PLL2 DLD is high, on Status_LD2 pin.

    For PLL1, with 25 MHz reference...
    VCO Frequency = Reference Frequency / PLL1_R * PLL1_N * DCLKout6_DIV
    VCO Frequency = 25 MHz / 119 * 476 * 15 = 1500 MHz. As such I expect PLL1 DLD is low.
    If you adjust your PLL1_N = 952, then I think you will see a PLL1 lock.

    Let me know if this solves your issue and if so, verify answer. Thanks.

    73,
    Timothy
  • 0 in reply to Timothy T
    Intellectual 425 points

    Fullscreen lmk04828_tics_nested_0-delay_iter_5.txt Download 
    R0 (INIT)	0x000090
R0	0x000000
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x01006F
R257	0x010155
R258	0x010255
R259	0x010300
R260	0x010422
R261	0x010500
R262	0x0106F0
R263	0x010711
R264	0x01080C
R265	0x010955
R266	0x010A55
R267	0x010B00
R268	0x010C22
R269	0x010D00
R270	0x010EF9
R271	0x010F05
R272	0x01106F
R273	0x011155
R274	0x011255
R275	0x011300
R276	0x011422
R277	0x011500
R278	0x0116F0
R279	0x011715
R280	0x01186F
R281	0x011955
R282	0x011A55
R283	0x011B00
R284	0x011C22
R285	0x011D00
R286	0x011EF0
R287	0x011F31
R288	0x01200F
R289	0x012155
R290	0x012255
R291	0x012300
R292	0x012402
R293	0x012500
R294	0x0126F9
R295	0x012700
R296	0x012878
R297	0x012955
R298	0x012A55
R299	0x012B00
R300	0x012C02
R301	0x012D10
R302	0x012EF1
R303	0x012F01
R304	0x01306F
R305	0x013155
R306	0x013255
R307	0x013300
R308	0x013422
R309	0x013510
R310	0x0136F0
R311	0x013711
R312	0x013821
R313	0x013903
R314	0x013A00
R315	0x013B78
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F09
R320	0x014000
R321	0x014100
R322	0x014200
R323	0x014311
R324	0x0144ED
R325	0x01457F
R326	0x01461B
R327	0x01473A
R328	0x014802
R329	0x014902
R330	0x014A02
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015401
R341	0x015500
R342	0x015601
R343	0x015700
R344	0x015801
R345	0x015900
R346	0x015A08
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016104
R354	0x016244
R355	0x016300
R356	0x016400
R357	0x01650C
R369	0x0171AA
R370	0x017202
R380	0x017C15
R381	0x017D33
R358	0x016600
R359	0x016700
R360	0x01683C
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017300
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53
    Hello timothy,

    I have adjusted the values as suggested by you.

    For PLL2 , with 100MHz VCXO - PLL2_R = 4 ; PLL2_N=60;PLL2_P=2 . With this PLL2 DLD is high.

    For PLL1 ,with ref clock of 25MHz, PLL1_R =1; PLL1_N=8;DCLKOUT6_DIV=15 . with this PLL1 DLD is low.

    Find attachement for PLL register file.

    Regards,

    K. Jaya Bharath Reddy