CDCM6208 DEMO problem

Meng jeffrey

Expert 2760 points

Hello!CDCM62086208 DEMO I'm testing.

Here's the question:

Using the 25MHZ vibrate on the board card to input the clock source, the PLL output clock is set.

The output clock is normal, the PLL lock indicator is bright.

Using other clocks (in practice, the reference clock is only 15.625 KHZ)

When I'm using 15.625 KHZ for the REF clock source, PLL can't lock (PLL lock)

What is the lower limit of the REF input clock for 6208?On the manual

No detailed instructions were found.

over 8 years ago

0 Puneet Sareen over 8 years ago

TI__Expert 8865 points

Hi Jeffrey

While using other reference clock, have you adjusted the PLL parameters? Have you adjusted the dividers so that the VCO is in the correct range. Have you adjusted the loop filter to have enough phase margin?
The minimum PFD input frequency as per the datasheet is 8kHz.

Best regards
Puneet

0 Meng jeffrey over 8 years ago in reply to Puneet Sareen

Expert 2760 points

Hello!When using 15.625 KHZ as the reference input, I set the interface for the parameters
The output 0-7 is set to 27M, 27M, 24.576 M, 148.35 M, 148.5 M, 200M.
The dividers are automatically generated, but the PLL display cannot be locked.
Can you provide the correct parameters for the dividers according to these requirements?In addition, 6208 pairs of inputs
Does the reference clock account for any requirements?

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CDCM6208 DEMO problem