Low Jitter clock distribution

Hello Asad,

the CDCM61001 + buffer IC will be a fine solution. You didn't indicate what signaling your inputs require. Is it LVDS, CML, LVPECL, or single-ended?

If it's LVDS, you could use the CDCMVD110: http://focus.ti.com/docs/prod/folders/print/cdclvd110a.html

TI is also about to release the CDCLVD1212: http://focus.ti.com/docs/prod/folders/print/cdclvd1212.html.

For CML, the best choice would be the CDCL1810: http://focus.ti.com/docs/prod/folders/print/cdcl1810.html. If you AC couple the output, this device can probably drive any other input stage as well.

For PECL, you would want to use the CDCLVP1212: http://focus.ti.com/docs/prod/folders/print/cdclvp1212.html or the CDCLVP110: http://focus.ti.com/docs/prod/folders/print/cdclvp110.html

If you need these 9 clock signals single ended, you could use a single ended buffer such as the CDCLVC1110: http://focus.ti.com/docs/prod/folders/print/cdclvc1110.html

Another alternative that leaves you with a single device solution for single ended clock signaling would be to replace the CDCM61001 with the CDCE62005: http://focus.ti.com/docs/prod/folders/print/cdce62005.html

The CDCE62005 allows you to configure any of it's 5 differential outputs to also operate single-ended, which gives you practically 10 LVCMOS outputs.

Best regards, Fritz

Hello Asad,

the distance of 7-inch should be absolutely no problem for an LVDS output driver. We use similar signaling for much greater distances. For example, the signal feeding the LCD monitor inside a PC is LVDS, and as you can imagine, does not only go across pcb but also fpc cabling. For data transmission & depending on the actual data/clock rate, LVDS signals can drive multiple meters of cable. I was trying to look at the A17x, and AM18x data sheet to find out details about the clock input requirements but my internet access has some issues right now and my computer freezes when I try to download a large document. What's the exact clock frequency you need to get out of the device? I suspect sub 200MHz, right?

For best jitter performance, you want to minimize any reduction of the clock signal rise- and fall time due to impedance missmatch (e.g. vias, trace width changes, GND reference layer crossings, etc). You basically need to do the best possible differential layout. Route these signals early on and mark them in your schematic as 100-Ohm differential transmission lines with matched intra-pair length. This means the trace length between the p and the n signal must match each other within a few mil. Avoid 90 degree turns. If you look at the CDC61001 EVM you can see how we layout traces. I understand you probably want to bring the traces into an inner layer of the pcb - that's ok. Just ensure you keep the 100Ω differential (e.g. loose coupling with 50Ω impedance of each tansmission line). Depending on your actual system you probably have the same routing restrictions for several other signals.

Also, please avoid any noisy signals (signals with either high edge rates and/or large amplitudes) to run in parallel nearby the clock lines to avoid any noise from coupling into your lines and causing additional jitter.

Overall this design portion using LVDS signals to drive different SATA buffers should not cause you problems.

Good luck with your design! Fritz

Hi Asad, you are welcome. If pcb layout with differential signals is a less familiar topic to you, you might enjoy looking over the following file (despite the document discussing DisplayPort technology, which is another standard utilizing differential signaling for data in computer systems).

0552.Texas Instruments DisplayPort Design Guide.pdf