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LMK03328: Questions on Power and VIM specifications

user4779049
Expert 2345 points
Part Number: LMK03328
Other Parts Discussed in Thread: CODELOADER

Hi Team,

Please advise me on the following questions related to the LMK03328.

Q1. Can OUTn_P and OUTn_N output the same polarity of clock when outputs are configured in
       CMOS mode?

Q2. When 1.8V CMPS outputs are expected, can the VDDO_n be operated with 3.3V supply
        or restricted to 1.8V?
        The data sheet describes as bellow. This may suggest that to output 1.8V COMS clock,
        VDDO_x can be either 1.8V, 2.5V or 3.3V.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8.12 1.8-V LVCMOS Output Characteristics (OUT[7:0])(1) VDD_IN / VDD_PLL1 / VDD_PLL2 / VDD_DIG = 3.3 V ± 5%,

VDDO_x = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = -40°C to 85°C, outputs loaded with 2 pF to GND
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Q3. Can you give us the Min and Max value of try-level input pins such as REFSEL, GPIO[3:1] pins.
        The datasheet specifies Vim typical value.
        However, without MIN and MAX value, you cannot design the application board.

Q4. The device has several outputs (OUT0_P/N to OUT7_P/N) and dedicated power supply pins VDDO_01/23/4/5/6/7.
      If some of the outputs are not used the corresponding power pins can be left open or must be
       tied to supply?

Q5. The datasheet specifies the power up sequence. Are there any restrictions among VDD_IN, VDD_DIG
       VDD_PLL1, VDD_PLL2, VDDO_01/23/4/5/6/7?
       Can they be up at nay order as long as they up monotonic, with in 100 ms, and PD up later than
      all Power rail?

Mita

  • 0
    TI__Expert 4415 points

    Hi Mita-san,

    1. Yes, the polarity can be controlled as shown in the following screenshot of Codeloader. To set the outputs in phase, set the two outputs to (+/+) or (-/-). For out of phase, set (+/-) or (-/+). Each individual LVCMOS output can also be disabled and set to Vol or Hi-Z. To reduce crosstalk, we recommend out of phase if possible.

    2.LVCMOS levels are fixed (2x 3.3V for STATUS[0:1] and 16x 1.8V for OUT[7:0]) regardless of VDDO voltage. Any VDDO voltage can be used- we recommend 1.8V to minimize power consumption.

    3. For min and max values see Vih and Vil in the same table (reproduced below). For the absolute min and max values, see the Absolute Maximum Ratings table (table 8.1 on page 7 of the LMK03328 datasheet).

    4. All VDDO pins should be powered even if the output block is not used. To reduce power consumption, the output block can be disabled by setting the corresponding registers.

    5. The outputs can be powered up in any order as long as all the restrictions in the datasheet are followed. The only note is that there is an error in the datasheet on the use of the PDN pin- an RC circuit should not be attached to this pin and it should be left floating instead. In rare cases an RC circuit could cause incorrect power sequencing on startup causing the device to not start- if this occurs the PDN must be toggled or the device power cycled to resume correct operation.

    Regards,

    -Tim

  • 0 in reply to Tim Chao Li
    Expert 2345 points

    Tim-san,

    Thank you for your prompt feedback.
    I can clear all of my questions.
    However, please allow me to confirm my understandings bellows.

    Q3. Can you give us the Min and Max value of try-level input pins such as REFSEL, GPIO[3:1] pins..

    => Does it mean that the VIM should be 0.4 < VIM < 1.4?

    Q5 Power up sequence.

      You recommend  “this (PD) pin and it should be left floating instead”

        => Can PD pin can be set Low at power up instance then turned to be High after all
           power rails are settled to operational level, by driven by a Power Good signal in regulator IC?


    Mita

  • 0 in reply to user4779049
    TI__Expert 4415 points
    Hi Mita-san,

    3. I believe this is correct although I will test this to confirm and update you.

    5. At this time we recommend just leaving the pin floating and letting the device auto-start up when it detects the correct voltages. There is a possibility that using the PDN to control the device powerup can cause the issue listed earlier. A datasheet revision is in progress to clarify this.

    Regards,
    -Tim
  • 0 in reply to Tim Chao Li
    TI__Expert 4415 points

    Hi Mita-san,

    Please disregard my last answer to Q3.

    3. The actual max/min value for Vim is 0.7V to 1.1V. At 0.6V and 1.2V, the 3-level pin will register as low and high, respectively. We recommend keeping the 3-level pin as close to 0.9V as possible for Vim.

    Regards,

    -Tim

  • 0 in reply to Tim Chao Li
    Expert 2345 points

    Tim-san,

    Thank you for the answers.

    I can  clear all of my questions.

    Mita