Other Parts Discussed in Thread: DAC38J84EVM
Hi Team,
I have a customer who is implementing a design based on the DAC38J84EVM and they are looking to utilize the clocking distribution strategy outlined in section 5.1 of the user's guide, specifically related to the LMK04828 conditioner.
In this case, an S/SD pair is routed to the FPGA, and a separate S/SD pair is routed to the DAC. Now, they understand that a S/SD pair needs to be matched. Are there any length matching requirements between the LMK->FPGA S/SD pair and the LMK->DAC S/SD pair that they need to be aware of?
Thanks for your help,
Mitchell