LMK04828: SYSREF request to sysref output deterministic latency

guy vaisman

Part Number: LMK04828
Other Parts Discussed in Thread: LMK04616

Hello,

I'm considering using the LMK04828 or LMK04616 clock distributors.

I would like to know if the latency between the moment the SYSREF REQUEST pin is pulled high
and the moment the SYSREF appears on the output and aligned to the device clock is deterministic?
Does is it happen after a fixed number of device clock cycles?

Please elaborate on the two components.

Thanks in advance,

Guy.

over 8 years ago

0 Puneet Sareen over 8 years ago

TI__Expert 8865 points

Hi Guy

What mode you will be using? Do you want to use it as a dual loop jitter cleaner and generate DEV/SYSREF pairs?
Also, is the SYSREF_REQ issued to the SYNC pin syncronous to the input clock or completely asyncronous?

Best regards
Puneet

0 guy vaisman over 8 years ago in reply to Puneet Sareen

Prodigy 230 points

Hi Puneet,

I'm interested in using it as a single pll (bypass the first PLL and don't use jitter cleaning) and generate multiple DEV&SYSREF signals. Also, before issuing the SYSREF_REQ i will use the SYNC option as well.

To your second question, the SYSREF_REQ and the input clock are both synchronous to the same 10MHz reference.

Thanks,
Guy.

0 Puneet Sareen over 8 years ago in reply to guy vaisman

TI__Expert 8865 points

Hi Guy

In this case, both devices will have deterministic latency relative to the SYSREF request.

Best regards
Puneet

Clock & timing

Clock & timing forum

LMK04828: SYSREF request to sysref output deterministic latency