Dear Team,
Please help to check if TI has the solution as below description.
The design is for PXI clock solution. PCH can output one pair of 100M clock (HCSL type. swing >300mV, VOL=0.8V, VOH=2V).
They need the solution which has one input and can output below 4 different types of synchronous clocks.
a. 3.3V, 100M LVPECL differential clock, 50ppm.
b. 3.3V, LVPECL differential PXIe_SYNC100 signal (10% Duty cycle of 10M Clock, for clock synchronization, the period is 100ns, High 10ns, Low 90 ns.)
c. 10M TTL clock (single-end, Voltage< 3.3V, VOH>2.4V, VOL<0.5V).
d. PXIe_SYNC_CTRL as below figure.
Detail of spec:
Thank you.
