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CDCLVD1208: State of the input will go to if the input connection is broken (unknown, High Z, valid/invalid ?)

Kishen Someshwar
Intellectual 1625 points
Part Number: CDCLVD1208

Hello Team,

I have a customer who is using the CDCLVD1208 in their design and has reached out with the following question :

For example, if the connection of positive signal of the differential pair (CLK_100_T/F) is somehow broken (open), what is the state of the input? Is it High Z, unknown, valid/invalid? How does this affect the output? Do you have any test reports for these type of cases?

From what I have read input can be left floating and so activity on the unused input will not propogate to the output ?

Can you please clarify the above doubt.

Thank you for your time and support.

Sincerely,

Kishen

  • 0
    TI__Mastermind 32575 points

    There is input failsafe / hysteresis to ensure the input does not self-oscillate or chatter when the selected input is left floating.

    In your use case, what is the bias condition on the negative input when the positive input is floated?  Is it biased, pulled-up, pulled-down, or floating?

    Regards,
    Alan

  • 0 in reply to Alan O
    TI__Intellectual 1625 points
    Hello Alan,

    Thank you for the information. In the customers use case, they have 100 MHz differential input clock connected to the differential input pins INP0/INN0. They would like to know what state (unknown, High Z, valid/invalid) of the input will go to if the input connection is broken. For example, what is the state of the input if one of the input (either the positive (INP0) or negative (INN0)) input of the differential input is broken (open). What happens if both input connection is broken. With the broken input condition, what is the output of the differential receiver will be? Will it be unknown, High Z, valid/invalid?

    Thank you for your time.

    Kishen
  • 0 in reply to Alan O
    TI__Intellectual 1625 points
    Update on the post :

    The negative input is biased when the positive input is left floating. There is a 100 ohm termination resistor across the differential signal (CLK_100_T/F) at the differential input pins. Would this have any effect on the state of the input if the negative input is biased and the positive input is floating?

    Since the input does not self-oscillate or chatter due to input failsafe, does that mean that there won’t be a valid (100 MHz differential) signal at the output if one input is biased and the other is floating?

    Sincerely,

    Kishen
  • 0 in reply to Alan O
    TI__Intellectual 1625 points
    Hello Alan,

    Can you confirm the behavior of the input as per my last post. The customer is curious to find out whether he could try this without any issues.

    Sincerely,

    Kishen
  • 0 in reply to Kishen Someshwar
    TI__Genius 16845 points

    Hi Kishen, 

    If the 100MHz clock is not supplied at power-up, the device inputs will be in an undefined state as the input differential voltage will be ~0V due to the 100 ohm resistor; consequently, the outputs will be pulled to ground.

    After an input clock that meets the specified input switching threshold is applied, the outputs will then conform to the specified LVDS output voltage levels.  If the input signal is removed, the outputs will remain at their LVDS output logic states.  

    In this application, there won’t be a valid clock signal at the output when INP0 is floating and INN0 is biased.  If you want to maintain a known output logic level whenever the input is removed, you may consider using weak external biasing on the differential inputs to provide a defined differential input logic state (low or high).

    Kind regards,

    Lane Boyd