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CDCM6208: CDCM6208 EVM software input requirement

NIBIN S
Intellectual 550 points
Part Number: CDCM6208

Hi,

I am using Clock synthesizer (CDCM6208V1RGZT) in my design. The clocks are interfaced to Vertex 7 FPGA as part of clock requirement by different interfaces, also for SRIO interface in transceiver bank. 

The output clock requirement is six 125MHz clock and two 200MHz clock.

I used EVM software tool for the synthesizer.

I need few input clarifications.

1) Phase margin

2) Loop Bandwidth

3) CP current

4) Gamma parameter

Please verify the attachments which shows the inputs for the design.

Please let me know the details ASAP.

Thanks and Regards,

Nibin

  • 0
    TI__Expert 8865 points
    Hello Nibin,
    Phase margin defines the PLL loop stability. >50 degrees is generally good. You can let the tool calculate that.
    Loop bandwidth defines the bandwidth of the PLL loop. The right value also depends on the input clock phase noise. If you are using 25MHz Xtal like proposed in the user guide, you can use loop bandwidth of 300kHz. CP current also effects the loop bandwidth and the filter components. For xtal as a reference clock input, you can use chargepump current of 2.5mA to calculate the loop filter. Gamma factor is the qualifyig factor for the PLL loop filter. Leave it upto the tool to calculate.
    In your Loop filter calculator snapshot, you should change the Charge pump current to 2.5mA and press "Suggest RC". You can also then press the "Phase Noise Tool" to see the simulated phase noise at the clock outputs.
    Best regards
    Puneet