Hi TI,
I'm trying to use CLKin0 at a LMK04828 to synchronize my clock outputs on multiple devices/boards (Differential input SYNC mode, a per datasheet pg.36).
My setup uses exclusively an external clock (CLKin1) and a common sync source which is synchronous to the system clock. The configuration of the relevant registers is as follows:
// Prevent any other source from generating a SYNC event
0x143 = 0xD0;
// Change the SYSREF_MUX to use CLkin0, Use SYSREF_CLKin0_MUX dedicated input
0x139 = 0x40;
// Enable Clkin0_OUT_MUX to drive the SYSREF MUX
0x147 = 0x00;
// Enable dividers reset
0x144 = 0x00;
After that I generate a software controlled pulse to synchronize reset the dividers and revert the changes in the SYSREF path as follows:
// Disable divider reset
0x144 = 0xFF;
// restore SYNC_MODE (no sync source)
0x143 = 0x10;
// Disable CLKin0_OUT_MUX (other than 0 is OK)
0x147 = 0x03;
// Change the SYSREF_MUX to use SYSREF continuous source
0x139 = 0x03;
I'm monitoring the SYSREF outputs from two LMK devices and the phase relationship between the two SYSREF is not consistent over time. I've tested the same setup using the SYNC pin and it seems to work just fine (of course the register configuration above gets a bit changed).
Is there any issue with this configuration for SYSREF synchronization?
Kind regards.
