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CDCLVP1204: Output about CDCLVP1204RGTR

Cris Qi
Intellectual 835 points
Part Number: CDCLVP1204

Dears,

     Customer Design:156.25m crystal oscillator +buffer:CDCLVP1204；electric level：LVPECL,

     Clock receiver input：Differential pk-pk0.4V-0.9V， CDCLVP1204:0.65V-1.35V，Current design according to the 150 ohm drop-down of series resistance and ac coupling capacitance manner of termination.

     I have some questions about it，

      1. Buff output is a range 0.65V-1.35V,what is the range is related to？ the ability to output level range, or device deviation range？

      2.By adjusting the way to adjust the output level of series resistance, what is the principle of the way？ the input impedance and load partial pressure？ need to meet ( buff output from 0.6 V to 1.35 V level fluctuations, after the partial pressure of output within the scope of 0.4 to 0.9 V)？

      3.Series resistance adjustment will affect the signal quality,? up and down time is less than 0.8 ns (20% - 80%), and the edge of the signal is Monotonic。

Wish to receive your reply ,thank you very much.

  • 0
    TI__Mastermind 32575 points

    1.  The Vout,diff,pp swing will depend on the operating frequency and over PVT.  See Figures 3 & 4, which show the Vout,diff,pp variation over frequency and low Vcc (2.5V-5% & 3.3V-10%).

    2.  A series resistor is an option to form a voltage divider with the receiver input / load termination (50 ohms single-ended), in case the receiver requires less swing than the output swing from the LVPECL driver.  I provided some app note references which discuss this.

    3.  Series resistance at the driver side (RS, up to ~50 ohms) could improve the signal integrity by providing better source impedance matching for 50-ohm traces, since the LVPECL driver output impedance is low.  But higher source impedance will reduce the swing at the receiver side due to the attenuation factor of (RL / (RS+RL)).

    App note references on LVPECL interfaces (as well as other differential signaling interfaces):

    Regards,
    Alan

  • 0 in reply to Alan O
    Intellectual 835 points
    So the CDCLVP1204:0.65V-1.35V diff to 0.325v~0.675v,cannot meet the recevier:0.4v~0.9v,it is ok?
  • 0 in reply to Cris Qi
    TI__Mastermind 32575 points
    At 156.25 MHz and 2.5V, the Vout,diff,pp should be ~1.15 Vpp typ. From Figure 3, Vout,diff,pp is ~0.9 Vpp at low Vcc and over temp.

    So, if you use Rs ~33 ohms (near driver side after 150 ohm pulldowns), then you would get ~60% (=50 / (33+50)) of the driver output swing at the receiver inputs (which should be terminated with 100 ohms differential). This would provide enough margin to meet the receiver input swing of 0.4~0.9 Vpp.

    Regards,
    Alan
  • 0 in reply to Alan O
    Intellectual 835 points
    For example, if the LVPECL output swing is 750 mV and the required receiver input is 400 mV, then
    the attenuation factor is 0.68, how to get 0.68？