LMK04828: SYNC pin with external reference clock

Hi Jasvir

Can you please draw a block diagram showing multiple LMK devices and how they are connected? Please also mention the corresponding frequencies.

Best regards

Puneet

Hi Puneet,

The system block diagram is shown next. It uses a master board which generates a 1GHz reference and distributes a SYNC signal using the LMK04828. The clock is properly distributed using a different clock buffer. To this master board there are several slave boards each of them with an LMK04828 and other JESD204B devices.

At each slave board, the LMK04828 is used as follows:

The SYNC signal is passed to the SYNC pin and routed all the way through the SYNC/SYSREF distribution path. The 1GHz clock reference is just used to generate SYSREF and passed to the DCLK outputs for other clock generation.

The synchronization sequence is as follows,

1) Once the LMK at each device has been configured with the default configuration I enable the SYNC path for resetting all the clock dividers (SYSREF included):

// Enable SYNC funtionality (one-shot, SYNC pin)
0x143 <- 0xD1

// Change the SYSREF_MUX to use SYNC input
0x139 <- 0x00

// Disable CLKin0_OUT_MUX (other than 0 is OK)
0x147 <- 0x03

// Enable dividers reset
0x144 <- 0x00

After doing this for all the board I generate a SYNC pulse. The pulse is generated by an FPGA and controlled by software. At the moment the pulse lasts for 100ms and it's generated with a clock synchronous to the 1GHz clock.

Once the pulse is done I restore the default configuration of the LMK at the slave boards:

// Disable divider reset
0x144 <- 0xFF

// restore SYNC_MODE (no sync source)
0x143 <- 0x10

// Change the SYSREF_MUX to use SYSREF continuous source

0x139 <- 0x03

After doing all this I would expect to have the SYSREF of all boards either aligned or show a consistent phase relationship from run to run but I can't achieve it and I'm a bit out of ideas. This setup for single boards but I don't seem to find a way to scale it.

To begin with, is this setup correct to achieve multi-board synchronization?

Looking forward to your reply.

Kind regards

Hi Puneet,

Thanks for your answer.

Could you elaborate a bit more on why SYNC is not recommended for this case? Would it help if my frequency reference is lower, let's say 10MHz? Unfortunately my Clkin0 input is AC coupled so I can't use it for resetting the dividers.

Regarding your document, it uses PLL2 0-delay configuration which is not compatible with Clkin1 driving the high frequency reference. My only option here would be nested 0-delay PLL which I guess I will make no difference. On the other hand, I can't warranty deterministic phase relationship between different boards if I use the clock dividers for DCLK outputs.

On the other hand, It would be great if I could generate SYSREF locally since the SYNC lines coming from the master are later used for a different purpose.

Kind regards

Hi Puneet,

I was wondering if the following setup would work given the fact that my Clkin0 is AC coupled:

Drive a subharmonic frequency reference of the lowest frequency generated by the LMK04828 at Clkin0 for clock synchronization. In my case my lowest frequency is SYSREF = 31.25 MHz so I'm thinking of 7.8125 MHz = SYSREF/4.

With that reaching all the boards I'll start enabling divider reset circuitry at all chips (sequentially). The point here is that no matter at which moment they get reset, the frequency relationship of all clocks makes all these moments the same. After some time, I'll start disabling the divider reset circuitry.

Does it make sense, or do the levels for AC coupled signals not work with the reset circuitry?

Kind regards