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LMX2571: settling time when changing output dividers?

ajayt
Genius 9555 points

Part Number: LMX2571

Hi Team

I'm using PLLatinum Sim to find the lock time for phase and freq error - 1deg and 1kHz

The model included VCO cal time and analog loop dynamic time.

However, for the frequency switching I want to do, will involve changing the output dividers.

Assuming we write these registers in the fastest time possible allowable by the lmx2571, can you tell me how fast the dividers switch and settle.

Example cases:

Fstart  Fstop
10MHz  1344MHz
500MHz 501MHz
1000MHz 1100MHz
500MHz 1000MHz

Regards

  • 0
    TI__Guru** 121440 points
    Hi Ajayt,
    As you know, the total lock time consists of (1) programming time (2)VCO calibration time and (3) analog loop lock time.
    If you need to change the output divider while switching to a new VCO frequency, then only (1) will be longer because of additional register write time.
    If the freq change is due to output divider value change only, there is no "lock time" involved, we only need to program the divider register. The response time of the divider is very fast, in ns range.