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LMK04828: How to sync two LMK04828 outputs?

min hu
Intellectual 990 points
Part Number: LMK04828
Other Parts Discussed in Thread: CODELOADER

I need 10 pairs of DCLK and SYSREF to serve 10 DAC chips.

DCLK = 156.25MHz,SYSREF = 19.53125MHz

a LMK04828 can provide 7 pairs of DCLK and SYSREF,so i need two LMK04828 in parallel.

Master Reference input:100MHz,the master LMK04828 provide 156.25MHz DCLK and 19.53125MHz SDCLK(continuous,used for SYNC input for slaves)

SYNC PIN and CLKIN0 PIN of master LMK are not used

my problem is:DCLK output of two slave LMK are not phase alligned.and no SYSREF output.

I use the Clock Configuration Tools to export register values,a SPI mater module in FPGA finish LMKs setting.

where did i wrong??

  • 0
    Intellectual 990 points
    and another question is:how to generate 10 SYSREFs of 19.53125MHz??
  • 0 in reply to min hu
    TI__Expert 5370 points
    Dear min hu,

    thank you for your detailed question. I will get back you shortly, thank you for your patience.

    Regards, Simon.
  • 0 in reply to Simon Damphousse
    Intellectual 990 points

    Hi,Simon

    there is no way to generate DCLK and SYSREF in the same time when SYNC function is needed, since SYSREF and SYNC shere the same path, the SYNC input should be a single pulse to reset all the DCLK output dividers,and SDCLK = SYNC,so SYSREF output must be a single pulse!

    i try to disable SYNC_EN bits by setting  reg  0x143[4]=0,and i also try to put on SYNC_DISSxx by writting reg 0x144=FF to ignore the rest SYNC pulse（SYNC input from CLKIN0 is 19.53125MHz continuous,output by master LMK）,but i failed,the synchronization state will be broken,i don't know why?

    i got SYSREF output by using CodeLoader not TICS pro to export reg values,that is strange because two tools have the same setting.no SDCLK output when using TICS pro reg values.

    SYSREF_MUX=Normal,DDLYx_EN must be OFF!! DCLK outputs seem to be sync(not expected sine,interrupt by further SYNC input),but there is a jitter between to slave LMK DCLK outputs  that can be observed(the green trace is thicker) ,

    below is a screen shot of Oscilloscope:

    no time to lose,maybe i should begin a new PCB design:one slave LMK output all the DCLKs for sampling clock with another output all the SYSREF??

    i need your advise,

    Thanks

  • 0 in reply to min hu
    TI__Expert 5370 points
    Dear Min Hu,

    I found a detailed document on synchronization using LMK04828 that I would like to share with you. You will likely find it very useful. Could you please e-mail to clock_support@list.ti.com. I will reply and forward the document then.

    Regards, Simon.