Problem: Large (~5dB) power fluctuations centered around 2220MHz and 4440MHz (.5-1MHz bandwidth). Dips are random within that bandwidth and change from ramp to ramp, but are always centered around these two frequencies. Output power on either side of this region is continuous (and data points within the bandwidth that aren't "dipping" are also continuous with power outside the region).
My assumption is that this is due to the VCO hopping between two separate cores at this frequency (the problem is clearly prior to the output dividers, which pretty much narrows it down to the VCO), but I can't find any documentation that lists the frequency ranges of the individual VCO cores. I searched through the July revision of the data sheet but didn't see any mention of this. I see that there is a register option to manually select the VCO core, but without frequency ranges this is somewhat useless. What bothers me, though, is the continuity of the power outside of these two center frequencies. These 5dB dips are localized. If it were an issue of two VCO cores having different output powers and the calibration routine simply oscillating between the two at a transition frequency, then I'd expect the power to not be continuous after the transition. PLL seems to maintain lock, so I don't think it's an issue with that.
