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LMK00338: Clock Phase Jitter

Jim CHEN
Expert 4795 points
Part Number: LMK00338
Other Parts Discussed in Thread: LMK03328

Dear Team,

My customer met a problem when testing the clock phase jitter.

Just like below figure, the test item is failed.

This clock is the source of BMC (PCIe gen2.)

Now they are trying to modify the damping resistor on LMK00338RTAR. Chang from 33ohm to 22 ohm.

But we still want to ask you have you ever seen this kind of issue?

Could we solve it by modifying the code of LMK00338RTAR?

 

Thank you.

  • 0
    TI__Mastermind 32575 points

    Can they share the screenshot showing the Clock Jitter Test Results window (e.g. Pass/Fail, High Frequency Jitter values, Low Frequency Jitter values)?

    Can they share the o-scope setup file?  The measurement result is very dependent to the o-scope settings.

    They should follow the following o-scope setup guidelines:

    •Real time acquisition, no interpolation
    •Minimum 160 uS/division(200 uS/division)
    •Minimum 12.5 Gs/s sample rate(25 Gs/s)
    •Vertical scale set to maximum 100 mV/div (50 mV/div can give better results)
    •4 GHz bandwidth
    •Capture Rising Edge

    Make sure they set the proper measurement reference point.  The most consistent reference is at the fastest part of the edge, which may deviate from the 50% level or zero-crossing point. 

    Can they send a screenshot of the single-ended (P & N) and differential (P-N) waveforms?  Keep probe tip wires as short as possible to minimize reflections.

    Regards,
    Alan

  • 0 in reply to Alan O
    Prodigy 190 points

    Hi Alan,

    As the subject is of Jitter, may I know what is the jitter of LMK03328 for frequencies between 50MHz to 150MHz. We are using AD9249 ADC in our design for which we have selected LMK03328 as the master clock source. The aperture jitter requirement of ADC AD9249 is 135fs.

    LMK03328 datasheet gives jitter as 150fs for output frequencies <100MHz and 100fs for output frequencies of >100MHz.

  • 0 in reply to Abhijit Pethkar
    TI__Mastermind 32575 points

    LMK03328 can achieve less than 150 fs RMS jitter for Integer PLL mode with clean 50 MHz input (such as a 50 MHz crystal or low-noise oscillator reference).

    Phase noise and RMS jitter performance can be simulated using WEBENCH Clock Architect.  You can refer to this web video tutorial series:

    Regards,
    Alan