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CDCLVC1310: Single Ended vs. Differential DC Characteristics

Christoph Larndorfer74
Prodigy 150 points
Part Number: CDCLVC1310

I intend to stage two CDCLVC1310, i.e. on part will be driven by the LVCMOS output of the other. I was wandering if I can use only series termination only?

The section for INPUT CHARACTERISTICS is ambiguous in the datasheet as:

  • for the "Single-Ended DC Characteristics" of the PRI_INP pin suggests, that I can feed in the LVCMOS signal with source termination only
    • High level should be smaller 3.3V+0.3V
    • Low level not below -0.3V
  • for the "Differential DC Characteristics" of the PRI_IN pins suggests, that I need to attenuate the 3.3V LVCMOS signal as
    • Differential input voltage swing has to be smaller than 1.3V (which would be around 1.65V for a 3.3V LVCMOS signal in PRI_INP with PRI_INN centered at 1.65V)

Which information is correct?

I know the datasheet recommends a Thevenin termination when coupling LVCMOS, however, I would like to understand why exactly this would be required if the source is already terminated. If it is done only to limit the output voltage swing, then could it be an option to use a 2.5V or 1.8V LVCMOS signal and adjust the input voltage for the PRI_INN pin accordingly?

Thanks.

  • 0
    TI__Mastermind 32575 points

    Since the input buffer is natively differential input stage, I suggest the single-ended LVCMOS input be compliant to both Single-ended and Differential DC inputs specs.

    Thevenin termination is one method to limit the input voltage swing from the driver and meet the input specs.  This method is suggested if you need 3.3V LVCMOS outputs from either buffer, since VDDO should not exceed VDD.

    As you mentioned, an alternative method is to use the 1st buffer with 2.5V LVCMOS output with source termination to drive the 2nd buffer stage's IN+ input and bias IN- input to 1.25V with VDD of 2.5V.

    Regards,
    Alan