CDCS502: https://e2e.ti.com/support/clocks/f/48/t/56357

Hello MVD
Like specified in the datasheet, onchip CL on Xin & Xout is 10pF. That means there is a 20pF capacitor on XIN & XOUT pins onchip. There two capacitors results in 10pF effective capacitor for Crystal.
You should look at the datasheet of the crystal you want to use to find out the CL requirement. If CL required is 10pF, there is no need for any other capacitor. If >10pF is required, then you should connect discrete capacitors offchip.
You can refer to this document for theory.
www.ti.com/.../slea071.pdf
Best regards
Puneet

I assume this is assuming that there is no stray or load capacitance

Let for instance say to work out the value of the external capacitance(Cx) for a crystal with a load capacitance (Cl), we would use the following equation.

Cl = (Cx + Cstray)/2

Cl = 18pf
Cstray = 20pF(CDCS502 load cap)
10pF = (Cx + 20pf)/2
Cx = (10*2) - 20
Cx = 0pF (For external Cap)

But if:

Cl = 18pf
Cstray = 20pF + 4pF(CDCS502 load cap + paracitic track and Crystal Capacitance)

18pf = (Cx + 24pF)/2
Cx = (18 x 2) - 24
Cx = 16pF (For external Cap)

Is my calculation Correct???

Thanks in advance

Martin