Part Number: LMK04610
Tool/software: WEBENCH® Design Tools
A customer I support is looking for a clocking solution for a JESD204B ADC connected to a FPGA.
They initially selected the LMK04610 for lowest jitter.
I proposed to also have a look at the Clock Architect, which they did.
Pls. Find below their comments.
The option “JESD204B compliant” is missing.
The weigh factors for priority settings do not work as expected.
If jitter is set to highest priority and the other 3 parameters set to low priority there is still a sorting on cost and
best jitter specs is at place 8
Is there a way to simulate the LMK04610?
