Other Parts Discussed in Thread: TEST2
Selected part of the PLL : LMK04828BISQE/NOPB
Input clock frequency at CLKin0 : 25MHz
All Device clock(Sampling Clock) output frequency : 125Mhz
All Sysref clock output frequency : 390.625Khz
PLL Simulation software tool : TICS Pro
Input frequency of the ADC : 160MHz (+/-20MHz)
We are using 16bit JESD204B supported ADC. With 160Mhz input frequncy, 390.625Khz SYSREF and 10dbm input power level, we found spuriuos signal at 390Khz symetrically towards both side of the center frequency in the FFT plot.
We have changed the configuration as power down configuration with the same conditions as described above. Then also the 390Khz signals are existing.
Then SYSREF frequency has been changed as 125Mhz with power down configuraiton inorder to confirm whether the 390.625 Khz Sysref frequency is causing spurious. With this configuraiton no spurious appeared at 390KHz from the center frequency.
Herewith i have attached the FT data based on the below different test cases.
Test Case 1:
Input frequency: 160Mhz
Input Power level: 10dBm
Sampling frequency: 125Mhz
SYSREF Frequency: 390.625Khz (ENABLE)
Result: Spurious at 390KHz from the center frequency
Test Case 2:
Input frequency: 160Mhz
Input Power level: 10dBm
Sampling frequency: 125Mhz
SYSREF Frequency: 390.625Khz (POWER DOWN)
Result: Spurious at 390KHz from the center frequency
Test Case 3:
Input frequency: 160Mhz
Input Power level: 10dBm
Sampling frequency: 125Mhz
SYSREF Frequency: 125Mhz (POWER DOWN)
Result: No Spurious at 390KHz from the center frequency
Kindly give the suggestion to avoid the spurious from the sampling clock (Device clock).
