WEBENCH® Tools/CDCM6208V2G: simulation at jitter cleaner mode on WEBENCH

Hi Shawn,

Thank you for reply.
I tried simulation on WEBENCH that conditions as follow;

==Conditions==

input frequency : 6.75MHz
Output frequency : 148.5MHz

==Results==

Loop bandwidth : 84.703kHz -> RMS Jitter : 641.1fs
Loop bandwidth : 0.987kHz -> RMS Jitter : 1073.3fs


Jitter-cleaner mode is more than higher jitter normal mode.
Why?

Regards,
ACGUY

Hi ACGUY,
It is possible.
Jitter cleaner is for a noisy reference. Jitter cleaner (narrow bandwidth) or clock generator (wide bandwidth) is a trade off for phase noise performance for reference, PLL (in band contribution phase noise) and VCO (out of band contribution phase noise).
When reference phase noise or PLL is better than internal VCO in some frequency offset, wide bandwidth would be better than narrow bandwidth. It is your simulation result.
But when you add more noise on reference, you would find narrow bandwidth is better.

Regards,
Shawn

Hi Shawn,

Thank you for your advice.

Last question;
I work in distributor at japan. I am full-time FAE of TI.
Our customer is designing new product at now.
Previously, this device was D-in in another design, they designing with reference it, but the FPGA will change to Kintex.
About the additional jitter of clock output by the FPGA, do you know approximate numerical values?
Please let me know the value according to your experience or knowledge.

Regards,
ACGUY

very thanks!