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CDCLVP111: CDCLVP111

Ofer Eyni
Prodigy 40 points

Part Number: CDCLVP111

Hello,

I need to supply several 250MHz clocks to several receivers with ultra low jitter between them.

receiver has LVDS input.

I read Application report SCAA059C, and on figure 5 it describes how to make the conversion from LVPECL to LVDS (attached).

my questions:

1. Does this conversion affect the jitter between synchronized outputs?

2. Does this solution fits 250MHz clock?

3. can the 10k Ohm resistors be placed close to the transmitter?

thank you

  • 0
    TI__Genius 9920 points
    Hi Ofer,

    1, This conversion circuits would not affect jitter performance much. There is no active component and R/C unbalance fact also is in control, so jitter almost is similar as original.
    2, 250 MHz is no problem when AC coupling cap is larger than 0.001uF.
    3, 10kOhm resistors bias circuits are for LVDS receiver, when the receiver didn't have internal bias. It can't be put before AC caps.
    If the receiver has its own LVDS bias, 2 pcs of 10 kOhm resistor could be removed.
    4, If LVDS receiver has an internal 100Ohm load, the external 100 Ohm resistor also could be removed.
    5, Make sure your LVDS receiver Vid (input amplitude) range could cover max LVPECL driver Vod (output amplitude). Normally LVDS receiver Vid is wide enough to cover LVPECL driver.

    Regards,
    Shawn