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LMK61E2: ultra low jitter clock solution for my application

xyz xyz
Intellectual 1000 points
Part Number: LMK61E2
Other Parts Discussed in Thread: LMK00304, LMK03806,

Hello

in my design I have a ZYNQ FPGA board. it can produce a clock signal base on the PLL-block. but I think the jitter is not low! so I can not use it to feed the high speed ADC/DAC.

I'm looking for a solution to keep the datasheet's spec and minimize the price/ pcb design/time...

I can have some plans as follow:

generating a clock using FPGA----->clock driver-----> 200MHz for the 14-Bit DAC (LVDS or CMOS)

                                                                           ------> 65MHz or 80MHz for the 14-Bit ADC (LDVS or CMOS)

using for example LMK61E2---> clock driver---> ADC/DAC/ plus to the FPGA bcoz I should synq the DAC with FPGA

using for example LMK61E2--->  ADC/DAC/  plus to the FPGA bcoz I should synq the DAC with FPGA

or other plans...

Do you have any suggestions? I need a certain and reliable solution.

Best Regards

  • 0
    TI__Genius 9920 points
    Hi,
    An XO (LMK61E2 or others) + buffer LMK00304 --- > LMK03806 & FPGA
    LMK03806 could generate clocks for ADC, DAC, or FPGA data process.
    FPGA could use a clock from buffer as a system clock, and program LMK03806.

    Regards,
    Shawn
  • 0 in reply to Shawn Han
    Intellectual 1000 points
    Dear
    I appreciate you for your recommendations and remarks
    actually the FPGA has its clock (I have a ZYNQ FPGA) and it's independent. I want to send a Synq or command bit by the FPGA into the clean clock generator to feed the DAC, ADC and FPGA again. (if I said FPGA again bcoz I want to synq FPGA with the DAC)

    FPGA has its clock and it's working and will send a command to the clock generator
    on the other hand I have the below clock generator:
    LMK61E2--->clock distributer------>DAC & ADC &FPGA

    is it a good plan?
  • 0 in reply to xyz xyz
    TI__Genius 9920 points
    Hi,
    It could work.
    If you used a buffer, the propagation delay can't be tuned, so Synq is no useful. Buffer outputs only have some skews each ohter.
    If you used a clock generator or clock jitter cleaner, Synq signal is useful to align clocks from different dividers.

    Regards,
    Shawn