Hi, Experts:
We are trying to interface with LMK04828 with 1.8V IO due to the limited resource of 3.3V IO in FPGA.
For the digital input signal of LMK, I think we need to make sure the MIN number of VOH of FPGA >1.2V and MAX number of VOL< 0.4V.
For the digital output signal of LMK, I can use a resistor divider like 10K series resistor and 12K shunt resistor to divide the 3.3V IO down to 1.8V.
Can you please help to double check if you see any issues regarding this?
Thanks a ton for your kind help
Yarn.