LMK04828: SYNC_MODE in section 9.3.3.3 Dynamic Digital Delay Example (as shown below)

Hello Chris
Please see my comments below:

Question 1:
I don't understand step 7 in this example. It seems like it sets the SYNC_MODE back to 2 after previously setting it to 3 in step 6. Elsewhere in the document it says that SYNC_MODE must be 3 to generate a SYNC event when writing the DDLYd_STEP_CNT register. Is there perhaps a typo in step 7?
A: SYNC_MODE should be kept 3 in step 7.

Question 2:
The documentation also says that the ONLY way to use dynamic delay is with writing the DDLYd_STEP_CNT register via SPI. Just to verify, you can NOT use the external SYNC input to execute the number of delay insertions currently specified in DDLYd_STEP_CNT ? It would make my design easier if I could use an edge mode SYNC input to insert DDLYd_STEP_CNT delays with each edge of the SYNC input.
A: The dynamic digital delays can only be applied using write to DDLYd_STEP_CNT.

Best regards
Puneet

I am attempting to delay the phase of the LMK04828 output clocks one VCO cycle at a time  using the 0x142 register.  Below is the register configuration for the part.  It is a list of 24 bit values written to the PLL via SPI.  The entries from 0 to 55 are written to initialize the PLL and then the entries from 57 to 62 are used to attempt to advance the phase on the enabled channels by 1 VCO clock.  

When I run the writes from locations 57 to 62, it produces a seemingly number of VCO clocks of phase shift. Sometimes it does 1, but many times it does more than 1.  The phase shift is monitored on an oscilliscope looking at the relative phase of the output clocks versus the reference input.

Do you see anything wrong with these register settings?

Do you have a verified sequence of register writes that can be used to increment a selected set of clock phases by one VCO clock?  My writes follow the example from the documentation, as far as I can tell, but they produce inconsistent results.

I would appreciate any help or insight you can offer.

0 => x"000080", -- Write RESET to 1

1 => x"010078", -- DCLKOUT0/USERCLK ODL/IDL high, 0x18 = divide by 24
2 => x"0101CD", -- Configure for 333ps (1 clock) of VCO clock of dynamic delay assuming divide by 24
3 => x"010671", -- Enable power to clock group 0/1 and digital delays
4 => x"010705", -- Power up DCLKOUT0 for +/- 800mv LVPECL
5 => x"010878", -- DCLKOUT2/GBLCLK ODL/IDL high, 0x18 = divide by 24
6 => x"0109CD", -- Configure for 333ps (1 clock) of VCO clock of dynamic delay assuming divide by 24
7 => x"010E71", -- Enable power to clock group 2/3 and digital delays
8 => x"010F05", -- Power up DCLKOUT2 for +/- 800mv LVPECL
9 => x"011078", -- DCLKOUT4/PRGCLK ODL/IDL high, 0x18 = divide by 24
10 => x"0111CD", -- Configure for 333ps (1 clock) of VCO clock of dynamic delay assuming divide by 24
11 => x"011671", -- Enable power to clock group 4/5 and digital delays
12 => x"011705", -- Power up DCLKOUT4 for +/- 800mv LVPECL
13 => x"011878", -- DCLKOUT6/GBLCLK ODL/IDL high, 0x18 = divide by 24
14 => x"0119CC", -- Configure for 0 VCO clock of dynamic delay assuming divide by 24
15 => x"011E71", -- Enable power to clock group 6/7 and digital delays
16 => x"011F00", -- Power down DCLKOUT6. Still used internally for Zero Delay feedback
17 => x"012078", -- DCLKOUT8/USERCLK ODL/IDL high, 0x18 = divide by 24
18 => x"0111CD", -- Configure for 333ps (1 clock) of VCO clock of dynamic delay assuming divide by 24
19 => x"012671", -- Enable power to clock group 8/9 and digital delays
20 => x"012705", -- Power up DCLKOUT8 for +/- 800mv LVPECL
21 => x"012878", -- DCLKOUT10/GBTCLK ODL/IDL high, 0x18 = divide by 24
22 => x"0129CD", -- Configure for 333ps (1 clock) of VCO clock of dynamic delay assuming divide by 24
23 => x"012E71", -- Enable power to clock group 10/11 and digital delays
24 => x"012F00", -- Power down DCLKOUT10
25 => x"013078", -- DCLKOUT12/DBCLK ODL/IDL high, 0x18 = divide by 24
26 => x"0131CD", -- Configure for 333ps (1 clock) of VCO clock of dynamic delay assuming divide by 24
27 => x"013671", -- Enable power to clock group 12/13 and digital delays
28 => x"013705", -- Power up DCLKOUT12 for +/- 800mv LVPECL
29 => x"013820", -- Select VCO1 for PLL2, disable OscOut to use ClkIn2
30 => x"013F09", -- Enable feedback mux for 0-Delay mode
31 => x"014000", -- Enable power for SYNC/SYSREF circuitry
32 => x"014157", -- Enable dynamic delay on DCLKOUT0/2/4/8/12, i.e all active clock outputs
33 => x"014319", -- Sync Mode. Level trigger sync from SYNC pin and PLL2 !LOCK
34 => x"014408", -- Disable SYNC events from affecting feedback clock DCLKOUT6
35 => x"01457F", -- Fixed Value Required
36 => x"01463A", -- Enable input buffers, set MOS for CLKIN1 and Bipolar for CLKIN0/2
37 => x"01472A", -- Manually select CLKin2 as the PLL1 reference input and route ClkIn0/1 to PLL1
38 => x"014802", -- Set CLKSEL0 to input
39 => x"014902", -- Set CLKSEL1 to input SDIO to push/pull in read mode
40 => x"015040", -- Disable holdover mode and force use of manual clock source enable
41 => x"015432", -- Set CLK0 input divider to 50 (0x32) for debugging
42 => x"015602", -- Set CLK1 input divider to 2
43 => x"015802", -- Set CLK2 input divider to 2
44 => x"015A19", -- Set PLL1 N divider to 25 to divide 125 MHz feedback to 5 MHz for comparison
45 => x"015B15", -- Set PLL1 4ns phase match window, positive slope, 550ua gain
46 => x"015F0B", -- PLL_STAT1 selects PLL1 Digital Lock Detect push/pull output (B). 5B for PLL1_N
47 => x"016104", -- Set PLL2 R divider to 4 for 500/4 = 125MHz PFD
48 => x"016290", -- PLL2 prescaler = 4, OSCin freq > 255MHz, doubler disabled
49 => x"0171AA", -- Fixed Value Required
50 => x"017202", -- Fixed Value Required
51 => x"017C15", -- Specify LMK04828 for OPT_REG_1
52 => x"017D33", -- Specify LMK04828 for OPT_REG_2
53 => x"016806", -- Set PLL2 N divider to 6. Combined with prescaler get 3000/24 = 125
54 => x"016E13", -- PLL_STAT2 selects PLL2 Digital Lock Detect push/pull output (13). 7B for PLL1_R, 23 for holdover
55 => x"017300", -- Make sure PLL2 powered up. Should default to powered up, but doc is not clear
56 => x"FFFFFF", -- EOF for initialization code
57 => x"014313", -- Set SYNC_MODE = 3 to allow pulser to trigger digital delay, clear SYSREF register
58 => x"013E00", -- Set one sync pulse. Not sure if this is necessary
59 => x"013902", -- Enable Pulser based SYNC
60 => x"014201", -- Program 1 steps of digital delay for 333ps
61 => x"014319", -- Set back to SYNC_MODE = 1
62 => x"013900", -- Return to normal SYNC
63 => x"FFFFFF" -- EOF

See the following reply about seemingly random clock phase when attempting to add one VCO clock of digital delay