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LMK03328: Driving SYNC pin high when PDN is low

Madhu Sharma
Expert 2915 points
Part Number: LMK03328

Hi,

For LMK03328 clock synthesizer, the SYNC Pin ( GPIO 0) is controlled using a CPLD in one of my designs.

This will cause the signal to be driven high during power-up for about 100ms ( until the CPLD gets configured). It will be driven low again after CPLD configuration.

 PDN pin will remain in low state in this time.

So Please let me know whether this kind of pulses in SYNC signal when PDN is low cause any reliability/functionality issues or device damage.

Thanks & Regards,

Madhu