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LMX2594: Input Reference Clock Jitter and Frequency requirements

Part Number: LMX2594


Hi,

I am planning to use LMX2594 in one of my designs. In the datasheet, typical characteristic graphs are given with various output jitter values.

- I would like to know what should be the input reference clock spec to meet these jitter values.

- Will the jitter response be affected by input reference clock frequency also.

I am planning to use an input reference clock of around 1GHz to get an output ranging from 10GHz to 15GHz. It is very critical for me to achieve the output jitter values similar to what is mentioned in the datasheet.

  • Kiran,

    Good question. The input reference clock phase noise is a very critical, especially as the LMX2594 has such low PLL phase noise. The input reference clock phase noise directly contributes to the PLL phase noise portion of the LMX2594 output.

    The formula I use to determine this is take the phase noise of the reference clock and add 20*log(output_frequency / reference_frequency). If this phase noise is the same level as what you see in the datasheet, it is pretty much double the amount of the same noise and you get about 3dB addition. Here are some calculations to give an idea:

    If the phase noise from the formula is:
    3dB below the LMX2594 phase noise, the total addition is about 1.76dB
    6dB below the LMX2594 phase noise, the total addition is about 0.97dB
    9dB below the LMX2594 phase noise, the total addition is about 0.51dB

    An example here for your case:
    You want 15GHz output
    input reference is 1GHz
    use the formula to find 20*log(15GHz / 1GHz) = 23.5dB
    from datasheet you see 15GHz carrier @ 100kHz offset, it is -84dB
    So if your 1GHz reference @ 100kHz phase noise is 107.5dBm/Hz, it will translate to -107.5dBm/Hz + 23.5dB = -84dBm/Hz and from above section you see that if the phase noise is equivalent, there will be about 3dB total addition, and at 15GHz carrier @100kHz offste, you'll see about -81dBm/Hz.

    Hope this helps!

    Regards,

    Brian Wang