LMK04208: Phase Noise Issue in Signle PLL Mode with PLL2 only, and Need Reference Configuration

KevinZhang123

Part Number: LMK04208

Hi, Team

My telecom customer is using LMK04208 in their MDAS project. They use signle PLL mode with PLL2 only. The spec is below:

Input: 25MHz single-ended with 0.4Vpp to OSCin.

Output: CLKout0&1&2&5 = 156.25MHz (LVDS), CLKout3&4 = 20MHz (LVCMOS single-ended, use OSCin frequency directly).

Loop filter configuration:

Customer find the phase noise of CLKout is big.

Could you share a reference configuration according to customer's spec?

Thanks

Kevin Zhang

over 7 years ago

0 Puneet Sareen over 7 years ago

TI__Expert 8865 points

Hello Kevin,
The output phase noise in the PLL2 mode also depends on the phase noise of the input clock. Please use the Webbench tool to optimize the loop filter based on the input clock phase noise.
Best regards
Puneet

0 KevinZhang123 over 7 years ago in reply to Puneet Sareen

TI__Expert 5750 points

Hi, Puneet

The Webench tool for LMK04208 use dual loop PLL (PLL1 and PLL2). How can I set it to single PLL mode?
Thanks

Kevin

0 Puneet Sareen over 7 years ago in reply to KevinZhang123

TI__Expert 8865 points

Hi Kevin
Just set the PLL1 bandwidth very low, enter 1M ohm & 100uF in the PLL1 loop filter. Then just set the VCXO phase noise with the phase noise numbers of your input clock.
Best regards
Puneet

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LMK04208: Phase Noise Issue in Signle PLL Mode with PLL2 only, and Need Reference Configuration