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LMK04828: PLLatinum Sim with external VCO

Gil Hershman71
Intellectual 630 points

Part Number: LMK04828
Other Parts Discussed in Thread: LMK04832, OPA209

hello,

We are using the LMK04828 with an external VCO and loop filter and the PLLatinum Sim software:

When defining an external VCO frequency outside the boundaries the PLLatinum states (2495 to 3205 MHz):
Does it calculate the loop filter correctly?

thanks

Gil

  • 0
    TI__Expert 8865 points
    Hello Gil
    I hope you are not mistaken. LMK04828 is not yet part of PLLatinum Sim software. The max VCO frequency of LMK04828 is 3080MHz. The one you are simulating is LMK04832. LMK04828 can be simulated in Webbench or Clock Design Tool. For External VCO, you can also select Custom profile in PLLatinum and do the loop filter calculations.
    Best regards
    Puneet
  • 0 in reply to Puneet Sareen
    Intellectual 630 points

    Hello Puneet,

    Indeed I am using the LMK04828.

    I am using the PLLatinum Sim software in the Custom profile, as you suggested.

    Each loop filter calculation, I get different results.

    I am attaching the three pictures I took of the filter designer results.

    Can you explain that?

    thanks

    Gil

  • 0 in reply to Puneet Sareen
    TI__Mastermind 28031 points

    Gil,

    I see you are using the custom PLL to model the LMK04828. For this design, there are two things to consider:

    1.  You are using an active type A filter.  For the active type A filter, The product of R1 and C1 is a constant, but one of them can be chosen freely.  So for this type of filter, typically, you should type a value for R1 or C1 into the fixed component box.   

    2.  You are using the power optimizer for the best jitter.   For this optimizer, it does use numerical methods and sometimes it can be tricked by local minima and it also bases this on the last design.  So in some cases, if you press the button a second time, it might find a slightly better solution.   Convergence issues become more challenging when working with boundaries and constraints  For instance, I see here that your phase margin is bounded between 40 and 60 degrees.  I think that this is likely the reason as the value for phase margin is close to this boundary.

    In general, if you use all the design inputs with the optimizer disabled, then you should get the same result every time, but the optimizer brings in challenges with convergence and local minima.  It's an extremely powerful tool, but not 100% bulletproof.

    Regards,

    Dean

  • 0 in reply to Dean Banerjee
    Intellectual 630 points

    Dear Dean,

    Although resolved, with your permission, I am adding two questions regarding the PLLatinum Sim software:

    1. The Kpd factor, as I understand it, should reflect the PFD output, which is proportional to the phase difference of input and VCO signal.

    Do I simply input the PLL2 charge pump sink/source current as programmed in the LMK?

    2. Usually, in other PLL devices, I know of an AUTO CAL sequence which is performed to calibrate the VCO to the frequency the PLL should lock on.

    In our case, using an external VCO (and loop filter), we don't do that. How do we "compensate" for that?

    3. I am adding the PLLatinum Sim output, which I used for the loop filter design. The loop filter response is a zero (minor fluctuations around 0V).

    I am adding the CPout2 waveform.

    Can you understand why? We use OPA209 with the filter design you see in the snapshot below.

    Thank you for your assistance !

    Gil