LMK04828: Output Phase Drifting with Nested 0-Delay Mode

user1896923

Prodigy 190 points

Part Number: LMK04828
Other Parts Discussed in Thread: CODELOADER

Hi:

I use an LMK04828 in a project with double-PLL mode, and Nested 0-delay mode also enabled, where:

CLKin1 as reference clock(REFCLK=12.5MHz) input of PLL1;

VCO of PLL2 chosed VCO1;

Then connect the output port SDCLKOUT7(configured as 25MHz SYSREF output) and DCLKOUT8(configured as 100MHz DEVCLK output) to a hispeed oscilloscope together with the original 12.5MHz REFCLK.

The oscilloscope screenshot showed that the 25MHz SYSREF output and 100MHz DEVCLK output are not phase-coherent with the 12.5MHz REFCLK input, and a time-drift of about 300ps existing,for example:

Where, the yellow line indicates the 12.5MHz REFCLK input, and serves as the trigger source of the oscilloscope;

The green line indicates the 100MHz DEVCLK output and the blue line indicates the 25MHz SYSREF output.

The screenshots above show that the DEVCLK and SYSREF output have "variable" phases compared with the REFCLK output(Just 3 examples show above, while in fact more phases exist).

SO, I want to know if there is any error in my configuration file ,or any other probable wrong leads to the phase-unalignment?

Looking forward to your answer, THANK YOU~~!

P.S.: my configuration file follows with several steps:

1st step: Reseting;

2nd step: setup clock output:

0x000090,

0x000000,

0x000200,

0x01006C,

0x010155,

0x010300,

0x010422,

0x010500,

0x010671,

0x010766,

0x01087E,

0x010955,

0x010B00,

0x010C22,

0x010D00,

0x010E71,

0x010F66,

0x01107E,

0x011155,

0x011300,

0x011422,

0x011500,

0x011671,

0x011706,

0x011868,

0x011955,

0x011B00,

0x011C22,

0x011D00,

0x011E71,

0x011F60,

0x01207E,

0x012155,

0x012300,

0x012402,

0x012500,

0x012671,

0x012706,

0x012878,

0x012955,

0x012B00,

0x012C02,

0x012D00,

0x012E71,

0x012F06,

0x013078,

0x013155,

0x013300,

0x013402,

0x013500,

0x013671,

0x013706,

0x013825,

0x013900,

0x013A00,

0x013B78,

0x013C00,

0x013D08,

0x013E03,

0x013F0D,

0x014001,

0x014100,

0x014200,

0x014311,

0x014400,

0x01457F,

0x014609,

0x01470E,

0x014802,

0x014942,

0x014A08,

0x014B16,

0x014C00,

0x014D00,

0x014EC0,

0x014F7F,

0x015003,

0x015102,

0x015200,

0x015300,

0x015402,

0x015500,

0x015602,

0x015700,

0x015896,

0x015900,

0x015A05,

0x015BD4,

0x015C20,

0x015D00,

0x015E00,

0x015F0B,

0x016000,

0x016101,

0x0162C4,

0x016300,

0x016400,

0x01650C,

0x017C15,

0x017D33,

0x016600,

0x016700,

0x016805,

0x016959,

0x016A20,

0x016B00,

0x016C00,

0x016D00,

0x016E13,

0x017300,

0x1FFD00,

0x1FFE00,

0x1FFF53

3rd Step: power up sysref & prepare sync

0x010670,

0x010E70,

0x011E70,

0x014000

4th step: reset sysref

0x014391,

0x014311

5th step:sync(with the sync pin; a sync pulse from external FPGA)

6th step: disable sync path

0x0144F7

7th step: set sysref continuous

0x013903

over 7 years ago

0 Puneet Sareen over 7 years ago

TI__Expert 8865 points

Hello
Let me look at your register configuration. Are you using TI EVM or a custom board?
How are you generating the register configuration, are you using Codeloader/TICSpro software?
Best regards
Puneet

0 user1896923 over 7 years ago in reply to Puneet Sareen

Prodigy 190 points

Hi:

We use the CodeLoader for register configuration generating.

A custom board used.

Looking forward to your reply & thanks!

0 Puneet Sareen over 7 years ago in reply to user1896923

TI__Expert 8865 points

Hello
Can you save the .mac file from codeloader and post it here?
You can do that from "File->save".
Best regards
Puneet

0 user1896923 over 7 years ago in reply to Puneet Sareen

Prodigy 190 points

Hi:

My .mac files are as follows.

Noted that every file was named with the step, and I only used part of every file to configure the chip, just as the original question described.

Looking forward to your further reply, and thanks a lot~!

mac files named with step.rar

0 user1896923 over 7 years ago in reply to Puneet Sareen

Prodigy 190 points

Hi:

I keep looking forward to your reply.

Thank you!:-)

0 Shawn Han over 7 years ago in reply to user1896923

TI__Genius 9920 points

Hi ,
1, Get PLL1 & PLL2 lock status.
Different register setting could show PLL1 or PLL2 lock status on below pins.
pin 31 Status_LD1, Register 0x15F PLL1_LD_MUX, PLL1_LD_TYPE
pin 48 Status_LD2, Register 0x16E PLL2_LD_MUX, PLL2_LD_TYPE

2, Yellow 12.5MHz slew rate is too slow, violated LMK04828 CLKin slew rate requirements : Min 0.15 V/ns, Typ. 0.5 V/ns
Can you provide a fast slew rate clock for CLKin ?
Another method you could try, set PLL1 R divider = 2, which would achieve a better slew rate for phase detector input, even though PDF would be reduced.

Regards,
Shawn

Clock & timing

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LMK04828: Output Phase Drifting with Nested 0-Delay Mode