CDCE18005: Phase noise plot for 10MHz clock

Hi, Mike here,

We're looking to use the CDCE18005 in a very low Phase Noise design to distribute a 10MHz clock.

Can you provide Phase Noise plot for 10MHz ?

Here are the specs we are trying to meet, ca you suggest the best part ?

Clock distribution 2 input Muxed to 5 outputs.

Voltage input = 0.4Vp-to-p   to   5Vp-to-p    (I'm thinking we night need to use a capacitive divider to reach these figures)

Phase Noise for 10MHz:

1Hz = -75dBc/Hz

10Hz = -110dBc/Hz

100Hz = -130dBc/Hz

1kHz = -140dBc/Hz

Vout = CMOS (2.5 to 3.3V in 50 Ohm load)

Thank you.

Mike Lorenz

Sr. Eng.