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LMK04828-EP: LMK04828

E G
Intellectual 400 points

Part Number: LMK04828-EP
Other Parts Discussed in Thread: LMK04828, ADC32RF45

Hello,

I am using LMK04828 to generate the sampling clock and accompanying sysref signal for ADC32RF45. Sampling clock is at 3GHz. Iam using DCLKout4-SDCLKout5 pair for device clk of 3GHz and sysref of frequency 2.34375 MHz respectively. I am wondering if there is any skew between DCLKout4 and SDCLKout5 that I should take into account. one other questin is that what does tsjesd204b = -80ps refer to in data sheet of LMK04828. Thank you for your helpful comments in advance.

  • 0
    TI__Expert 8625 points
    Hi EG,

    For the skew between the DCLKout4-SDCLKout5 pair you would look at the |Tskew| spec for the any pair same format row. The spec describes that typical condition the skew between the two outputs will be less than 50ps.

    For the ts[JESD204B] that describes the starting setup time of the SYSREF signal to the Device clock edge given those conditions in that row in electrical specs (this number differs depending on the condition). If you go to section 9.3.4 describing SYSREF to Device Clock alignment, this tells you how you can adjust this to a difference between SYSREF to Device clock needed for your system.

    Regards,

    Brian Wang
  • 0 in reply to Brian Wang
    Intellectual 400 points

    Hi Brian,

    Thank you very much for the quick response. I have couple points still not clear in my mind. I'd appreciate if you can clearify these points too.

    First one is that, in the data sheet skew is shown for fclk=245.76 MHz and my frequency of operation is 3GHz thus, do I get any skew different than 25ps? Also does this mean that SDCLKoutY is always delayed by at most 25 ps with respect to DCLKoutX of the same pair?

    Second point to be clearified is related to ts[JESD204B]. Does this mean sysref always leads device clk by 80 ps? Also in section 9.3.4 what does the line " it is possible to digitally adjust the SYSREF up to 20 VCO cycles before the SYSREF" mean?

    Thanks again Brian,

    Erdal

  • 0 in reply to E G
    Intellectual 400 points
    I am still waiting an answer. I'd appreciate if you can help.
  • 0 in reply to E G
    TI__Expert 8625 points
    EG,

    For the first section, the skew difference comes from the slightly different paths of each clock and thus different propagation times. Even at different signal frequencies, these signals will be delayed by this mechanism the same way thus that same spec applies to the 245.76MHz or your 3GHz frequency. 25ps is characterized for the longest pair, so that can say other pairs should be less than this time.

    It is expected that the sysref leads the device by 80ps all the time. That description actually has a typo we just found. It is 20 half VCO cycles. So the usefulness here is for example you have a 3GHz signal, 333.3ps period, at the beginning sysref lands at 80ps before one of the 3GHz signal's rising edge. If you want the sysref to be located in a different place in relation to your 3GHz signal, you can do a digital step (166.7ps) and adjust this so that now it is 86.7ps after that same 3GHz signal rising edge. And this can be done 20 times.

    Regards,
    Brian Wang
  • 0 in reply to Brian Wang
    Intellectual 400 points

    Thanks Brian, That helps alot.