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LMK04828: LMK04828

E G
Intellectual 400 points

Part Number: LMK04828

Hi,

In the data sheet revised on December 2015, on page 19 there is this skew value between DCLKoutX and SDCLKoutY given for fclk=245.76MHz. My frequency of operations are 3GHz  and 2.34375MHz for DCLKout and  SDCLKout respectively. Both of these signals belong to the same pair. For this case what skew do I get between  these signals? It is really hard to tell by looking at the data sheet because in the data sheet skew is shown for fclk=245.76 MHz. 

Secondly, on the same page ts[JESD204B] is given to be -80ps. Does this mean that sysref always leads device clk by 80 ps and thus appropriate and intentional delays between these signals should be introduced keeping this 80ps lead time in mind? Also in section 9.3.4 what does the line " it is possible to digitally adjust the SYSREF up to 20 VCO cycles before the SYSREF" mean?

I'd appreciate if you can clearify these points too.

Erdal

  • 0
    TI__Expert 8615 points
    Hi EG,

    For the time skew, there is a very specific condition listed in the datasheet to document the exact setting the test was performed. Since this is an electrical propagation time delay, the same property should be expected for other Fclk frequencies as well.

    For second point, yes, the sysref typically leads the device clk by 80ps, then for the digital adjust, I see why it is confusing, there is a typo, you can actually do 20 x HALF steps to adjust and each are in increments of 0.5 x [1/VCOfreq]. So for example if you take the 3GHz VCOfreq, then 1/3GHz = 333.3ps, and you can adjust from -80ps in steps of 166.6ps (20 times). This can help modify the placement of the SYSREF edge in different locations in respect to the device clock. Hope this clarifies!


    regards,

    Brian Wang
  • 0 in reply to Brian Wang
    Intellectual 400 points

    Thanks Brian,

    This helped a lot.

  • 0 in reply to Brian Wang
    Prodigy 15 points

    Dear Brian Wang

    hi,

    I'm  learning lmk04828,

    I would like to ask, I am configuring lmk04828, the external reference input 100M, pll1 R=120, N=120, pll2 R=1, N=12. Output 2.4G, but the phase noise is very poor. The output spectrum is as follows. What causes it?

    Regards

    yongkang