CDCM6208V1F: Prescaler A/B and SYNCN

Hello gf,

Here are answers to your questions:

1.

Does prescaler B synchronize with prescaler A when using SYNCN ?

No, Sync between prescaler A&B is not guaranteed unless they have the same value.

2.

When SYNCN signal been asserted, will Prescaler_B(PS_B) be in reset state until deassertion of SYNCN?

If yes, which timing will PS_B be enabled and restarted?

The prescalers keep on running, only outputs dividers are synced and restarted.

3.

In CDCM6208V1F datasheet page.65 "11.2.1.16.6 Output Synchronization",

it said as follow:

*************************************************************************

When SYNC is asserted (VSYNCN ? VIL), all outputs are disabled (high-impedance)

and the output dividers are reset. When SYNC is de-asserted (VSYNCN ? VIH),

the device first internally latches the signal, then retimes the signal with

the pre-scaler, and finally turns all outputs on simultaneously.

*************************************************************************

I want to know when all divider will be enabled and restarted.

When SYNC is asserted, are all divider(integer, fractional divider of A side / B side) be disabled and reset?

If yes, which timing will it be enabled and restarted?

Is it between 9 to 11 PS_A clock cycle after SYNCN deassertion( which is same timing as output get turned on)?

With SYNC, all the output are disabled, dividers are reseted and then outputs are enabled. The sync is internally synchronized to the  prescaler clock.

4.

When using SYNC signal, will Output of A side(Y0,Y1,Y4,Y5) and B side(Y2,Y3,Y6,Y7)

be enabled at same timing (based on PSA clock cycle)?

This is true if the PS_A & PS_B are set to the same value. If not, then there will be an additional uncertainty on the B side due to PS_A & PS_B not synced to each other.

I hope this helps, let me know if you have additional questions.

Best regards

Puneet