CDCE62002: pll is not locking.

yogesh tripathi

Prodigy 140 points

Part Number: CDCE62002

Hi ,

I'm trying to configure cdce62002, which have 148.5Mhz as input and generate output of 150Mhz.

following are the parameters:

REGISTERS
0 12B60050
1 B799E401
2 00000002

PORTS
0 DD
1 FF
2 DF
3 F9

INPUTS
PRI 148.50
AUX 0

EXTERNAL COMPONENTS
C4 6.8n
R4 2k
C5 180p

SPI write/read are verified.

My problem is PLL is not locking. Is the issue with parameters? or can anyone suggest any test case.

Thank-You in advance.

over 7 years ago

0 Alan O over 7 years ago

TI__Mastermind 32575 points

The settings look reasonable. Did you confirm the AC-coupled LVDS input clock is valid and stable? Did you try triggering the VCO calibration after input is valid/stable? Is the SYNC de-asserted? Are you testing this on the EVM or in your system board?

Alan

0 yogesh tripathi over 7 years ago in reply to Alan O

Prodigy 140 points

"Did you confirm the AC-coupled LVDS input clock is valid and stable?"
yes it is stable.
"Did you try triggering the VCO calibration after input is valid/stable?"
Not tried till now, will look into it.
" Is the SYNC de-asserted?"
I'm only programming reg0 and reg1.
"Are you testing this on the EVM or in your system board?"
On custom board.

0 yogesh tripathi over 7 years ago in reply to yogesh tripathi

Prodigy 140 points

Thank-You @Alan
It is working after a vco calib cycle(0->1) after reg write, and setting sync to 1 .
Just one thing, i'm also giving rom write. So again a vco calib need to be given after power cycle?

0 Alan O over 7 years ago in reply to yogesh tripathi

TI__Mastermind 32575 points

VCO calibration automatically triggers after power-on reset, so you may need to explicitly trigger it (by /PD pin or software bit) if the PLL reference input clock is not stable during the initial calibration.

Alan

0 yogesh tripathi over 7 years ago in reply to Alan O

Prodigy 140 points

Thank-you Alan for your reply.

Clock & timing

Clock & timing forum

CDCE62002: pll is not locking.