LMK04610: LMK04610

yeshayahou Baracassa

Part Number: LMK04610
Other Parts Discussed in Thread: LMK04616, LMK04828,

Hi TI

In my design i will use a clean input clock passed straight to PLL2 (unused PLL1).I'm conserned of noise increase when operating during vibration.

Are there any envinroment tests done on the device? such as vibration ,shock,humidity.

Thanks

Yeshayahou

over 8 years ago

0 Puneet Sareen over 8 years ago

TI__Expert 8865 points

Hello
Please send your request to support@ti.com. Our quality team will respond.
Best regards
Puneet

0 yeshayahou Baracassa over 8 years ago in reply to Puneet Sareen

Prodigy 200 points

Hi!
PLL2 include a VCO to perform all the output clocks .This VCO can generate addition phase noise when operating under vibration or shock that the PLL loop filter can not overcome .So the outputs clocks generated will suffer of more jitter.Did you have test results about this issue?
Thanks
Yeshayahou

0 Puneet Sareen over 8 years ago in reply to yeshayahou Baracassa

TI__Expert 8865 points

Hi Yeshayahou,
This device does not have any external loop filter. The PLL architecture is semi-digital with low analog vco gain. So the performance under vibration or shock events should be much better compared to the traditional PLL based devices. Unfortunately we do not have such performance data.
Best regards
Puneet

0 yeshayahou Baracassa over 8 years ago in reply to Puneet Sareen

Prodigy 200 points

Hi puneet

Maybe there is such data on similare devices with the same VCO technology like LMK04616 or LMK4828 ?

Thanks

Yeshayahou

0 Puneet Sareen over 8 years ago in reply to yeshayahou Baracassa

TI__Expert 8865 points

Hi Yeshayahou,
Please have a look at this application report:
www.ti.com/.../snaa296.pdf
I cannot say that it is one to one with LMK04610 or LMK04828, but this device also has a PLL with similar VCO technology. You can see that the vibrations sensitivity is really good. I hope it helps.
Best regards
Puneet

0 yeshayahou Baracassa over 8 years ago in reply to Puneet Sareen

Prodigy 200 points

Hi puneet
I have look at this application report and indeed the jitter vibrations sensitivity is low (~4ps rms) , but using this clock as ADC sample clock is still too noisy and will decrease the SNR (acceptable jitter values are around 0.2ps ).I think to perform a test to know the jitter influence.
Thanks
Yeshayahou

0 Puneet Sareen over 8 years ago in reply to yeshayahou Baracassa

TI__Expert 8865 points

In terms of jitter in such environment, we cannot say that you will get same sensitivity. This is still the worst case. The report was for Oscillator chip which has Xtal integrated with silicon chip that has a LC-VCO based PLL. To really check the performance, these tests should be performed. Unfortunately, we dont have such data to share with you.

Best regards

Puneet

0 yeshayahou Baracassa over 8 years ago in reply to Puneet Sareen

Prodigy 200 points

Hi Puneet

You right,i think to work only with PLL2 (using the VCO) with a stable reference clock supplied from external.In this way i hope that the VCO jitter will be low.

Thank you very much for your help.

Yeshayahou

Clock & timing

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LMK04610: LMK04610