Dear all,
one of my AA has configured the LMK04828 in distribution mode in order to have the following configuration:
The clock signal enters in CLKin0 and comes out as it is on DCLK8. The SYSREF signals which are enabled from a LVCMOS signal are generated from the input clock (128x divider).
The SYSREF signal is a burst of 8 pulses.
The SYSREF signal will be present at SDCLK 5, 7, 9, 11, 13
I've attached the configuration file. can yuo please double check it ?
thanks,
Domenico
R0 0x00080
R257 0x10155
R260 0x10420
R262 0x106F9
R265 0x10955
R268 0x10C20
R270 0x10EF9
R273 0x11155
R276 0x11420
R278 0x116F8
R281 0x11955
R284 0x11C20
R286 0x11EF8
R289 0x12155
R292 0x12420
R294 0x126F0
R297 0x12955
R300 0x12C20
R302 0x12EF8
R305 0x13155
R308 0x13420
R310 0x136F8
R313 0x13902
R314 0x13A00
R315 0x13B80
R316 0x13C00
R317 0x13D00
R318 0x13E03
R320 0x140F2
R321 0x14100
R323 0x14352
R324 0x14480
R325 0x1457F
R369 0x171AA
R370 0x17202
R380 0x17C15
R381 0x17D33
R323 0x143D2
R323 0x14352
