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CDCM61001: Question about oscillator input and frequency shift

Guru 19645 points
Part Number: CDCM61001

Please let me know about two points below for CDCM61001;

①If in the use case of Oscillator input (to XIN pin), Is there required or recommended jitter spec?

②When need to shift output frequency after startup and PLL locked, I think that way to stable the frequency shift is set the output divider only change, is it correct?

 If this idea is unstable, please let me know about way to stable setting.   

Best regards,

Satoshi

  • Dear Satoshi,

    good question.

    #1) there is no recommended jitter specifications for the reference however here are some thing you will want to consider. Inside the loop bandwidth of this device the reference phase will scale (20*log10(Fout/Fref) without attenuation from the control loop. The control loop will obviously attenuate the noise from the reference otuside the loop bandwidth. So if you look at the phase noise performance for your use case, it should guide you to select the right reference. You will also want to select the correct integration BW for your use case.

    #2) Here I assume you would like to change the output frequency with the output divider only so you do not lose lock. You may do this by using the 3 OD pins (13,14,15).

    I hope this helps.

    Regards, Simon.
  • Simon-san

    Thank you for reply,
    Sorry for addition, is there influence output jitter from input jitter(Oscillator)?
    I think that output jitter is below equation, is it correct?
    Jitter_out = Jitter_in × f_out / f_in

    Best regards,
    Satoshi
  • Satoshi-san,

    on your first question: yes there is. noisy reference will show on output INSIDE the loop bandwdith of the PLL. Once you integrate that noise you get the jitter.

    The equation you have there is not quite right. sorry this is not as simple as that .

    Regards, Simon.