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CDC3RL02 and clock jitter

John Orlando
Prodigy 20 points
Other Parts Discussed in Thread: CDC3RL02

Hello,

We're currently in the process of evaluating options for a design where we need to generate a clean, low-jitter square wave to feed a 100 Msample/sec A/D converter from a clipped-sine wave TCXO.  I recently came across the CDC3RL02 sine-to-square wave converter chip, and this appears to be an ideal solution.  Couple of questions here:

1) Is there an eval board for this part available?

2) All of the examples of the datasheet show a 1.8 Vpp sine wave coming in, and a 1.8 Vpp LVCMOS signal coming out.  I'd like to confirm that, as the spec section indicates, if we feed it a 0.8 Vpp clipped sine wave input, that we'll get a 1.8 Vpp LVCMOS output.

3) The additive jitter spec defined in the datasheet is 0.41 pS RMS.  Can I assume that this applies regardless of input type (clipped sine, sine, or LVCMOS)?  We're obviously sensitive to any additional jitter, as it affects our overall SNR in the A/D converter.

4) The datasheet specs a minimum input signal swing of 0.3 Vpp.  Are there jitter/phase noise specs available for lower voltage swing values such as this?

5) We don't need the LDO included in the chip, but it will be enabled whenever we enable either of the clock outputs.  Is there anything we need to do on this output line to make it happy/stable if we aren't using it?

 

Thanks much for any feedback you can provide for the above.

 

Regards,

John

 

 

 

  • 0
    TI__Genius 9085 points

    Hi John,

    1. Yes, there is an eval board available. We are currently waiting on assembly, but should be able to ship you one in about a week.

    2. Yes. The output is a 1.8V square wave regardless of the input amplitude.

    3. The datasheet specs additive jitter for an LVCMOS input (0.37ps RMS) and for a sine input (0.41 ps RMS.) Additive jitter is a function of the edge rates. A square wave will have the lowest additive jitter while a low amplitude sine wave will have the worst jitter.  The additive jitter for a clipped sine wave will be similar to a full scale sine wave.

    4. We did not spec jitter/phase noise below 0.8V. The part was designed for functionality to 0.3V, and signal integrity to 0.8V.

    5. The LDO requires a load capacitance of at least 1uF for stability.  Since the supply tends to be the dominant source of noise for single-ended systems, increasing this load capacitance will actually help improve the additive phase noise (and hence, jitter) of this device. More information can be provided on this, per request.

    Please let me know if I can clarify or there are further questions.

  • 0 in reply to Hattie
    Prodigy 20 points

    Hi Hattie,

    Thanks for the response.

    Re #1: I'm very interested in the eval board to allow me to make some measurements with our TCXO.  Let me know what I need to do to make this happen.

    Re #4: Just so I'm clear: is the load capacitance required even if the LDO isn't being used to power an external device?  It sounds like you're saying it is, due to noise on this regulator leaking into the actual clock buffer and adding phase noise.  If the internal LDO is used to provide power to the clock buffer as well as providing a regulated 1.8V for an external device, then this makes perfect sense.  If there is additional info that you think is relevant, I'd appreciate it.  Otherwise, I'll incorporate the 1uF cap and we should be set.

     

    Regards,

    John

  • 0 in reply to John Orlando
    TI__Genius 9085 points

    Hi John, 

    1. Please e-mail me about the board. h-spetla@ti.com

    2. Yes, the load capacitance is required even if the LDO isn't being used to power an external device. The LDO powers circuity internal to the clock buffer in addition to supplying the external 1.8V intended for a TCXO.

     

  • 0 in reply to Hattie
    Prodigy 10 points

    Is there a similar/same clock buffer with only one channel available instead of two?

  • 0 in reply to Marko Bundalo
    TI__Mastermind 20900 points

    Hello Marko,

    we do not have such a buffer as a one channel device, but you can use the CDC3RL02 and disable one output via the control pins CLK_REQ1 or CLK_REQ2.

    best regards,

    Julian