Dear Team,
our customer would like to use the CDCE62002 as jitter cleaner for a high speed interface reference clock @ Artix 7 FPGA (some more specs, see below).
They have to reduce the jitter from 100ps rms down to 1ps rms.
>> Is the CDCE62002 a good option for those requirements, or can you recommend another solution?
Looking forward to your feedback.
Best Regards
Martin
https://www.xilinx.com/support/answers/44549.html
|
Ref Clock Frequency (MHz) |
Phase Noise at Offset Frequency (dBc/Hz) |
|||
|
10 kHz |
100 kHz |
1 MHz |
||
|
100.0 |
-126 |
-132 |
-136 |
|
|
125.0 |
-123 |
-131 |
-135 |
|
|
156.25 |
-121 |
-129 |
-133 |
|
|
250.0 |
-119 |
-126 |
-132 |
|
|
312.5 |
-116 |
-124 |
-131 |
|
|
625.0 |
-110 |
-119 |
-127 |
|
