Hello,
My customer has a question about LMK04828.
[Q]
Is it appropriate for Lock Status of PLL1 to become Unlock once when input switching is performed under the following conditions?
<conditions>
- CLKin1 = 122.88MHz
- CLKin0 = 122.88MHz
- The phase difference between the two inputs is 0 ns.
- Input Clock Switching = Manual Mode
Although the Lock Status of PLL1 becomes unlock at the time of switching input, it is not a problem in particular.
I would be happy to tell you if you have any comments.
Best Regards,
Kaede Kudo
