Part Number: LMK04828
Other Parts Discussed in Thread: LMK04821
I am using LMK04828 on a dual site ATE final test board. With 700MHz/13dBm input at CLKIN1, I didn't see any output at SCLKOUT. Schematic is attached. Below are the SPI writes.
SPI::wspi_lmk(0x138, 0x40); //VCO mux = CLKIN1
SPI::wspi_lmk(0x146, 0x10); //CLKin1_EN = 1
// Divider of DCLKoutX_DIV
SPI::wspi_lmk(0x110,0x04); //S1 FPGA REFCLK_1
SPI::wspi_lmk(0x100,0x04); //S1 FPGA REFCLK_2
SPI::wspi_lmk(0x118,0x04); //S2 FPGA REFCLK_1
SPI::wspi_lmk(0x130,0x04); //S2 FPGA REFCLK_2
// Output Format
SPI::wspi_lmk(0x107,0x11); //S1 FPGA SYSREF = LVDS, REFCLK_2 = LVDS
SPI::wspi_lmk(0x10F,0x60); //S1 DUT SYSREF = LVPECL 2000mV
SPI::wspi_lmk(0x117,0x04); //S1 FPGA REFCLK_1= HSDS 10mA
SPI::wspi_lmk(0x11F,0x04); //S2 FPGA REFCLK_1= HSDS 10mA
SPI::wspi_lmk(0x127,0x60); //S2 DUT SYSREF = LVPECL 2000mV
SPI::wspi_lmk(0x137,0x11); //S2 FPGA SYSREF = LVDS, REFCLK_2 = LVDS
SPI::wspi_lmk(0x12F,0x00); //NC powerdown
// PowerDown
SPI::wspi_lmk(0x116,0x30); //S1 FPGA REFCLK_1
SPI::wspi_lmk(0x106,0x30); //S1 FPGA REFCLK_2
SPI::wspi_lmk(0x11E,0x30); //S2 FPGA REFCLK_1
SPI::wspi_lmk(0x136,0x30); //S2 FPGA REFCLK_2
// Select SDCLKOUTy input
SPI::wspi_lmk(0x104,0x20); //S1 FPGA SYSREF
SPI::wspi_lmk(0x10C,0x20); //S1 DUT SYSREF
SPI::wspi_lmk(0x124,0x20); //S2 DUT SYSREF
SPI::wspi_lmk(0x134,0x20); //S2 FPGA SYSREF
// Sysref divider
SPI::wspi_lmk(0x13A, 0x1); //div by 480
SPI::wspi_lmk(0x13B, 0xE0);
HSX_helper::StartHsxClk(4, Freq, 13); //LMK_CLKIN: 13dBm
WAIT_TIME(100 us);
SPI::wspi_lmk(0x144, 0xFF);
SPI::wspi_lmk(0x139, 0x3);
//power up
SPI::wspi_lmk(0x02, 0x0);