Other Parts Discussed in Thread: ADC12DJ3200, LMX2582, , LMK04828, TIDA-01410
Dear Sir,
Already we are using the 2 nos of ADC12DJ3200 device by providing common clock from LMX2582 and validated the phase synchroinzation between these two chips using SYSREF & Tapd.
Now, my requirement is by placing the two ADC's(replacing with 4Gsps part) and changing the clock scheme two 2 nos of LMX2594 & 1 LMK04828 for different sampling frequencies and phase synchronization.
My doubt is,
1. Whether this will be possible with my approach.
2. I am not getting clear information how to synchronize the ADC using SYSREF and SYNC from LMX2594 & LMK04828 in case of different sampling frequencies.
3. I gone through application note "Multichannel JESD204B 15-GHz Clocking Reference Design for DSO, Radar, and 5G Wireless Testers" I have doubts in this,
3.a can i proceed in nested 0- delay mode with external VCXO instead of single loop PLL.
3.b. No clear information regarding SYSREF generation, whether LMK04828 is generating sysref or lmx2594 is generating?
3.c. If LMK04828 is generating SYSREF/SYNC. Whether this is contionous/Periodic/pulsed?
Kindly help me regarding this.
Regards,
Bharath
