LMX2571: FM over-deviation issue at 2kHz modulation with 7Khz deviation in Synth mode

Joe Grigonis said:

Part Number: LMX2571

This issue occurs whether using Fast FSK (writing reg 33) mode or writing all 23 bits of the numerator directly (reg 17-18). 

Issue details:

1 - Writing a clean digitally generated sine wave to reg 33 at a 16Khz 160 kHz rate with 7k max deviation produces a clean 7k deviation signal for sine waves up to 1.5kHz -- from 1.5kHz to 2.2kHz, the deviation on receiver shows the LM2571 starts to over-deviate with a peak over-deviation at 2kHz sine wave input -- demod shows 7.6-7.8kHz deviation. 

2 - Writing static values to reg33 works perfectly fine and moves the carrier properly based on that static value written.

3 - This issue is apparent on all center frequencies tested.

4 - We are using F2, and I have tried changing charge pump currents and gain (R41, R40); as well as R value of 4th pole, 3rd pole internal loop filter and PFD_delay_F2 (R23, R22); as well as the order of the Delta Sigma Modulator (R20); no changes had an effect (changed values singularly to both extremes and a mid point).

5 - Issue is apparent but much less magnitude at 5kHz deviation -- issue results in 5.15kHz deviation at demod. 

6 - Issue is not apparent at 2.5kHz deviation.

Any further insight or direction is greatly appreciated!

Joe

I updated #1 above to reflect that the update rate to R33 is actually 160 kHz, not 16 kHz.  Sorry for the typo.

Hi Joe,

Since you've got correct deviation at <1.5kHz fmod, I think your PLL configuration and loop filter are set correctly. In theory, you should be able to get the same performance at other fmod frequencies. I don't have a good answer to your question, I think this is likely due to your codes.

FYI, I can generate the same deviation at different fmod.

With the exception of an internal RF related coupling issue in the PWB, we have fully isolated/localized the issue to the LM2571.  This fact is based on the following data: a running peak detector at the SPI interface always shows the max value being written to R33 is NEVER above 7000.  I can reset the peak detector and it immediately goes up to roughly 7000, never above and this is the same level it goes to whether we see 7.8kHz deviation (at 2kHz) or 6.99kHz deviation (at 1kHz).  Furthermore, we see the exact same issue whether generating the sinusoid using our internal tone generator (FPGA) or via an audio input to the FPGA using an external signal generator.  The issue is identical and again the value to R33 never goes above 7000. 

You are the expert, we were hoping an expert would be open-minded (like all excellent engineers) and consider that what we are stating might actually be true without us having coding problem?  ...and think what could potentially cause this, and keep thinking this until an insight came to mind?  This is not an answer I would expect in 10seconds, but would hope an expert on this device would let this resonate within their knowledge and be determined to, at some degree, to develop an insight linking a scenario (based off reg settings, rates, etc) which could lead to this issue -- and maybe even build upon ones knowledge of this part in this process.  Obviously your test works, but obviously there are some variables that differ in our setups as what you see we certainly do not see.

Can you please send us how you are configuring the device?  ....as well as rates you are updating R33 (assuming you are running in same mode).  ...and any other pertinent test related information that you can think of?  Also, do we have to re-write to reg 0 after updating a loop control variable or is that only after changing N-divider?

Again, our indisputable embedded fault localization and performance monitoring circuits as well as Xilinx Chipscope (embedded signal analyzer) all point to the issue being related to the LM2571.  Any and all considerations of what could cause this are very much appreciated.