Hi Team,
I have two questions using the reference doubler.
Q1). Can we still use doubler with input clock which has worse duty cycle distortion than 0.5% ?
Q2). To suppress this spurs, what do you mean by utilizing R3 and C3 ? I believe you would need to tighten the loop bandwidth. Why not external R,C components ? R3 and C3 is enough ?
I believe if the duty cycle is not 50%, doubled clock would have much more unstable clock. From this reason it seems to have spurs.
Best Regards,
Kawai
