This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK03328: Reference Doubler

Guru 19785 points
Part Number: LMK03328


Hi Team,

I have two questions using the reference doubler.

Q1). Can we still use doubler with input clock which has worse duty cycle distortion than 0.5% ?

Q2). To suppress this spurs, what do you mean by utilizing R3 and C3 ? I believe you would need to tighten the loop bandwidth. Why not external R,C components ? R3 and C3 is enough ?

I believe if the duty cycle is not 50%, doubled clock would have much more unstable clock. From this reason it seems to have spurs.

Best Regards,

Kawai

  • Hello Kawai-san
    Please find my comments below:
    Q1). Can we still use doubler with input clock which has worse duty cycle distortion than 0.5% ?
    A: Yes, doubler can still be used, but the worst duty cycle will result in higher reference spurs.

    Q2). To suppress this spurs, what do you mean by utilizing R3 and C3 ? I believe you would need to tighten the loop bandwidth. Why not external R,C components ? R3 and C3 is enough ?
    A: All depends on the level of suppression needed and what phase noise is acceptable inband. lowering the bandwidth will result in more noise from the VCO, that might result in worst rms jitter compared to not using the doubler. On the other hand, as the spur is at reference frequency, using higher order poles in the PLL transfer will damp the reference spur better, without lowering the PLL bandwidth.
    Best regards
    Puneet
  • Hi Puneet-san,

    Thanks for the support.

    Best Regards,
    Kawai