LMK04616: About digital system clock

Toshiyuki

Part Number: LMK04616

Hi,

I understand the PLL2REFCLKDIV Register controls the PLL2 Reference Clock Divider value for digital system clock. Then, what is the digital system clock for?

Best Regards,

Toshiyuki

over 7 years ago

0 Puneet Sareen over 7 years ago

TI__Expert 8865 points

Hello Toshiyuki-san
PLL2 digital logic runs with a internal boot oscillator at startup, after that, the boot-oscillator is powered down and the clock from the PLL2 input is used for digital. This is done to avoid different frequencies in the chip which might create additional spurs. PLL2_RDIV & PLL2_REFDIG_CLKDIV are parallel paths. PLL2_RDIV divider controls the phase detector frequency for PLL while PLL2_REFDIG_CLKDIV controls the frequency to the digital logic.
Best regards
Puneet

0 Toshiyuki over 7 years ago in reply to Puneet Sareen

Mastermind 7075 points

Hi Puneet-san,

I understand as follows. Is it correct?

Best Regards,

Toshiyuki

0 Puneet Sareen over 7 years ago in reply to Toshiyuki

TI__Expert 8865 points

Hi Toshiyuki-san,
The green path is after PLL2_REF_CLK block. That means if doubler is enabled then the clock going to digital is of 2x frequency.
Best regards
Puneet

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LMK04616: About digital system clock