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LMK04828: PLL issues on warmup

Part Number: LMK04828


Hi!
I have a custom board with LMK04828 in dual PLL mode, CLKIN0 = 120MHz reference, manual select, OSCin = 240MHz VCXO. PLL1 PDF = 20 MHz, loop BW = 100Hz. Holdover enabled, hitless switch enabled, automatic holdover on PLL1 LOL, MAN_DAC enabled with default value. System works fine until warmup up to ~65..70 Celsius (6-layer PCB temerature, measured 1.5mm off LMK's corner). It switches correctly to and from holdover, holds lock with reference frequency drift (it's stable but for checks) etc. But after it reaches "critical" temperature it looses PLL1 lock and enters holdover. It relocks after being slightly blown with freezer or just short touch with a finger. After I erroneously wrote 0x40 into 0x15C register (with 0x00 in 0x15D) the system changed it's behaviour. After reaching "critical" temp it drops DLD1 status but in fact keeps lock with reference, tracks drifts, CP1 output stays stable, signal spectrum of LMK's outputs is fine and matches that of a locked state. But with such a config LMK does not go into automatic holdover after loosing reference in the "hot" state (in "cold" it's ok with holdover). What could be wrong with PLL1? Power supplies are ok, low-noise, schematics similar to EVM's, separate supplies for clock outputs and VCXO.

TIA,

Sergey

  • Hello Sergey,
    Please post your register file (TICSpro file preferred) for review.
    Best regards
    Puneet
  • R0 (INIT)	0x000090
    R0	0x000010
    R2	0x000200
    R3	0x000306
    R4	0x0004D0
    R5	0x00055B
    R6	0x000600
    R12	0x000C51
    R13	0x000D04
    R256	0x01000E
    R257	0x010178
    R258	0x010255
    R259	0x010305
    R260	0x010420
    R261	0x010500
    R262	0x010630
    R263	0x010711
    R264	0x010807
    R265	0x010999
    R266	0x010A55
    R267	0x010B05
    R268	0x010C00
    R269	0x010D00
    R270	0x010E35
    R271	0x010F01
    R272	0x01101E
    R273	0x011155
    R274	0x011255
    R275	0x011300
    R276	0x011400
    R277	0x011500
    R278	0x0116FD
    R279	0x011700
    R280	0x011818
    R281	0x011955
    R282	0x011A55
    R283	0x011B00
    R284	0x011C00
    R285	0x011D00
    R286	0x011EFD
    R287	0x011F00
    R288	0x012007
    R289	0x012144
    R290	0x012255
    R291	0x012305
    R292	0x012420
    R293	0x012500
    R294	0x012630
    R295	0x012755
    R296	0x012807
    R297	0x012944
    R298	0x012A55
    R299	0x012B05
    R300	0x012C20
    R301	0x012D00
    R302	0x012E30
    R303	0x012F55
    R304	0x013007
    R305	0x013144
    R306	0x013255
    R307	0x013305
    R308	0x013420
    R309	0x013500
    R310	0x013630
    R311	0x013755
    R312	0x013800
    R313	0x013900
    R314	0x013A02
    R315	0x013B00
    R316	0x013C00
    R317	0x013D08
    R318	0x013E00
    R319	0x013F00
    R320	0x014000
    R321	0x014100
    R322	0x014200
    R323	0x014391
    R324	0x014400
    R325	0x01457F
    R326	0x014606
    R327	0x01470A
    R328	0x01481B
    R329	0x014933
    R330	0x014A02
    R331	0x014B16
    R332	0x014C00
    R333	0x014D04
    R334	0x014E04
    R335	0x014FFF
    R336	0x015013
    R337	0x015100
    R338	0x015220
    R339	0x015300
    R340	0x015406
    R341	0x015500
    R342	0x015606
    R343	0x015700
    R344	0x015806
    R345	0x015900
    R346	0x015A0C
    R347	0x015BD6
    R348	0x015C20
    R349	0x015D00
    R350	0x015E00
    R351	0x015F0B
    R352	0x016000
    R353	0x016102
    R354	0x016268
    R355	0x016300
    R356	0x016400
    R357	0x016507
    R369	0x0171AA
    R370	0x017202
    R380	0x017C15
    R381	0x017D33
    R358	0x016600
    R359	0x016700
    R360	0x016807
    R361	0x016959
    R362	0x016A20
    R363	0x016B00
    R364	0x016C00
    R365	0x016D00
    R366	0x016E26
    R371	0x017300
    R8189	0x1FFD00
    R8190	0x1FFE00
    R8191	0x1FFF53
    
    Hello Puneet,

    Attached is a basic setup, some SYNC and PD's are changed during operation but they are not related to PLL's.

    BR,

    Sergey

  • Hi Sergey,
    Did you check how much phase margin you have for PLL1. I am just thinking that if your phase margin is too low, you might start seeing issues.
    which VCXO are you using? please let me know the gain of the VCXO.
    Also, is the behavior dependent on PLL1 settings?
    Best regards
    Puneet
  • Hello Puneet,
    The calculated PM is around 70 degrees, I did not found any dependencies between this strange behavior and loop settings. I had tried different bandwith, pump current and so on. Seems like a switch - the system is stable, stable, stable and then immediately unlocked. And with that erroneous 6th bit in 0x15C register it is not even unlocked really - but lock is not detected somehow. Current setup uses Vectron's VS-720 VCXO with 13 kHz/V transfer.

    BR,
    Sergey

  • BTW, non-related to the problem, just a little finding playing with powerdowns an so on. If I turn off unused CLKin1_OUT_MUX (Reg 0x147[3:2]=0x3) power consumption rises up for 10 mA.
    Also, TICSpro exports register file with "spare" registers 0x102, 10A, 112, 11A, 122, 12A and 132 ))
  • Hi Sergey,
    Sorry I am out of office. I would suggest to send your request to clock_support@list.ti.com and one of my collogue should help you on that.
    Best regards
    Puneet